Jfet Buffer with bipolar supply.

[Chugs]

If I have a bipolar supply set up can I take advantage of that when using a fet buffer. Like this?

Bias to ground instead of vref and source resistor to -9v instead of ground.

[Gurner]

Put the bottom leg of your 1M gate resistor to -9V too (not to ground as in your drawing) ...essentially, your -9V is your virtual ground for the purposes of considering that FET biasing.

the way you've got it it, the jfet gate will always be about 8V or 9V *positive* relative to the source (whereas for a 'N' JFET you actually want the gate to be negative relative to the source).

[Chugs]

Thanks. I wasn't sure whether to put the 1M to ground or -9V.

[ECistheBest]

you probably want gate to be at 0v. source is actually near 0v, depending on the source resistor. this is a common drain configuration. you all know how when you have a 0~9v source follower you want to put the gate at 4.5v to have the most headroom?

[PRR]

IF supply is bipolar, I like + to Drain, zero to Gate, Source through resistor to -.

The source will float up to around 2V above gate. Supply current is about (2V+9V)/10K = 1.1mA.

Input cap may not be essential. Output cap is.

I'd also put several dozen K in series with the gate, close to the device, to limit radio and static discharge.

[Chugs]

I have a 10k resistor in series with the cap to the gate. I should have shown that on the diagram. My apologies.

This is how I have it set up on the breadboard. I have 8.98V on the drain. -8.11V on the gate and -8.41V on the source. The fet is a 2SK117.


image sharing

[kingswayguitar]

cool. 18v jfet circuit. dont you mean -8.41 on the gate and -8.11 on the source?

[Chugs]

No, the source is higher than the gate.

[ggedamed]

As it should.

You may want to read again PRR's message. Being a buffer (no amplification) your first version will work better, especially since your JFET looks like it has Vp (VGSoff) around 0.4-0.5V. Look what happens.

Gate to GND:



Gate to -9V:



I chose a rather extreme input voltage of 5Vpp, but the limiting in the second case occurs as soon the input voltage reaches the Vp value.

[kingswayguitar]

No, the source is higher than the gate.

True
And since -8.11 is closer to positive territory than -8.41, what I said was true. It's like when I work with p-jfets. Like a double negative.

[Chugs]

Well, the first sim looks better doesn't it! Ok, I put the 1M to ground as I had originally. I now have 89.8V on the Drain. 0V on the gate and -312mv on the source. 0V on the gate makes way more sense.

@ kingswayguitar. Yes, sorry. I got confused by the negative and positive voltage when replying. Doh!

[PRR]

> I now have 89.8V on the Drain

Almost Ninety Volts? I hope not!

> 0V on the gate and -312mv on the source.

With negative 9V and 10K?

We expect a small positive voltage. 1V, 2V or so. (Less for the FET you used.)

However this assumes the FET can pass all the current demanded.

That Idss is greater than source current.

You have 9V-0.3v= 8.7 volts, across 10K, should be 0.87mA.

> The fet is a 2SK117.

Datasheet says Idss can be 1.2mA to 14mA.

So a worst-spec '117 should easily pass the 0.87mA that this circuit demands.

Some curve-squinting says Source should be zero to 0.8V +positive+ of gate and ground.

While 0.3V negative "works", it will overload quite easily.

Take the source resistor up from 10K to 33K or 47K, see what happens.

[Chugs]

Sorry, it helps if I post the correct voltages!

+8.98V on the Drain. 0V on the Gate and +312mV on the Source.

Raising the Source resistor to 33K changes the source voltage to +0.419V and 47K changes it to +0.434V

[Gurner]

Re the earlier sim results/screenshots   ...those results differs wildly from what I get with an actual physical circuit that I've just this moment thrown together on breadboard (well, it's only 4 components...so it's quicker than knocking up a sim!)

With the gate to tied -9V through a 1M resistor, here's the input as applied to the gate....



& here's the output as seen on the source (source resistor is 10k, jfet is a J309...cos that's all I've got handy)...



So there you have it, both options work (that'll be the source resistor working as expected).

The reason I suggested connecting the gate to -9V via a 1M resistor is because (to my mind at least!) if you're running off batteries, it ought to yield more consistent biasing over the voltage 'drain curve' of the battery.

(btw: the scope traces above were with a more modest (& more guitar-esque) 1.8V pk to pk input signal  - but I did crank the signal input up to 5V pk to pk & observed the same)

[MetalGuy]

This is a very informative article on JFETs (including a section on bipolar PS buffers) from Erno Borbely:

http://www.raylectronics.nl/pdfs/Audio_Electronics_JFETs.pdf

Check the buffer section ( Part 2) and note the gate is always connected to ground, not (-).

[ggedamed]

Re the earlier sim results/screenshots   ...those results differs wildly from what I get with an actual physical circuit that I've just this moment thrown together on breadboard (well, it's only 4 components...so it's quicker than knocking up a sim!)

With the gate to tied -9V through a 1M resistor, here's the input as applied to the gate....



& here's the output as seen on the source (source resistor is 10k, jfet is a J309...cos that's all I've got handy)...



So there you have it, both options work (that'll be the source resistor working as expected).

The reason I suggested connecting the gate to -9V via a 1M resistor is because (to my mind at least!) if you're running off batteries, it ought to yield more consistent biasing over the voltage 'drain curve' of the battery.

(btw: the scope traces above were with a more modest (& more guitar-esque) 1.8V pk to pk input signal  - but I did crank the signal input up to 5V pk to pk & observed the same)

Differs wildly? Hmm...
J309 has VGSoff between -1 and -6.5V -1 and -4V. Did you measure it? I'm expecting that your JFET has more than 5V on the source (or should I say more than -4V). What is the voltage on the source?

[ECistheBest]

headroom for the negative half of the input signal depends on the pinchoff voltage (Vgsoff) of the JFET. if you raise the gate bias voltage to 0v (from -9v), you dont have to worry about the pinch off voltage since the source CAN swing quite a bit wider.