Sources of DC leakage?

[tempus]

I'm using a JFET switching arrangement in my current switching matrix (looper) setup like the one below:


It's fairly quiet, but I still get some switching pops (especially when bypassing the effect). It's not on the shem, but I have a cap on the gtr input. I'm looking for sources of DC that may be causing the pops. Would there be any leakage from the JFETs? If so, where should I put caps, i.e., between each JFET? What values should I use (I'm assuming I would make the last calculation based on the 1M resistor to ground, but I'm not sure).

A related question - I'm thinking about switching the JFETs  for H11F1's to get more isolation. In this case, each JFET would be replaced by one H11F1. Would there be a possibility leakage from these also?

Thanks

[duck_arse]

be nice to your fets. tie all their channels to a ref V, like V+/2, through high value resistors and isolate all your incoming and outgoing signals with caps. it seems to work for boss. have a look at rg's tube screamer technology of, it might become clear.

[tempus]

Thanks for your reply duck.

Sorry, that last schematic isn't the one I wanted. Here's the correct one with the improvements you've suggested:


The channels of all the JFETs are already held to ground. Does it matter if it's ground or V+/2? Also, I've added the caps where I think you meant. I didn't have caps going to and from the FX, because it would have blocking caps in there anyway. I've added them here though. Also, do you mean put caps between the sources and drains of each JFET? I'm still not sure about the values, but I think I should be using 1M in the F_c formula. Is that correct?

Thanks again

[brett]

Hi
regarding the "does it matter if it's gnd or V+/2", it depends on the quality of each.
If gnd is carrying more than a small amount of current, I'd be tempted to go with V=/2, as long as it has a low resistance AC path to ground. Usually, that means a large cap (eg 100uF) in parallel with a small film cap (eg 0.1uF).
cheers

[psychedelicfish]

Your second schematic doesn't have the caps to ground from the control voltages (the 0.047uF ones). You should include these because they take some time (with 0.047uF caps and 1M resistors as shown, the time will be 47mS) to charge up, which means that the switching of your FETs is slowed down enough to stop audible pops happening.

[duck_arse]

tempus, if you know the blocking caps are "in there already", fine. don't get caught. your caps as shown are correct for signals. the original caps on the control lines will help, as psych says. I've only ever seen circuits with the fet channels biased "up" to something/somewhere above ground. no to caps between S and D.

p channel fets make me nervous, as I've never had my hands on any. I'd better re-read technology of ....

at 1M, 22nF caps should just about cover guitar ok, I think.

[tempus]

Thanks again for all the replies everyone.

Psychfish - Good point - I actually forgot to redraw them in the 2nd schem...

Duck - thanks for all the concise answers to all of my questions. The purpose of biasing a JFET at 1/2V+ is to raise its operating point above 0VDC as far as possible to give maximum headroom for the signal without going over the 9V. If the guitar signal exceeds either of these, there will be clipping. It's not necessary to do this with a J176, however. As far as I know (and correct me if I'm wrong) biasing at 1/2V+ has nothing to do with switch pops.

[duck_arse]

mmmm, well, we are confusing biasing and biasing.

fets can be run in either the triode region or the pinchoff region. I've read rg keen describe this somewhere on this site recently, but I could only find the following link:

http://www.diystompboxes.com/smfforum/index.php?topic=54308.20;wap2

in one instance we can bias the channel and switch the gate on/off, more or less, and in the other, we bias the gate to minimise/maximise the distortion in an amplifying configuration. at least, that's what I've understood.

by biasing the channels, drains and sources are all at the same DC potential. the caps isolate the signal, and are ground referenced at their other ends. this means everything is at some fixed potential, there are no sudden changes when states change, and hence no popps. pops/popping is another good search term on this site