Layout Tips

[davent]

They're 100n (0.1 µF) axial ceramics from Digikey.

Something similar to these.

http://www.digikey.ca/product-detail/en/C420C104K5R5TA7200/399-4491-1-ND/818348

[tubegeek]

similar to these.

(Emphasis added.)

davent isn't dumb enough to let us know the exact mega-mojo ceramic bypass caps HE uses, 'cause he's found the only ones that won't add a subtle veil (flavored a bit like a dry Italian dessert wine, but with hints of mahogany and Petri dish agar) to the sound. Those, he's keeping for himself.

Sorry - I've spent way too much time on high-end audiophile forums in my day - it kind of gets under your skin.

[R.G.]

The exact capacitance value is not all that critical. 0.01 to 0.1 are probably OK.

I remember the advice for memory chip arrays back when 64K BIT memory chips were used in computers was to put 0.01uF and 0.1uF on every other chip. The idea there was to use 0.1uf for fast, local decoupling, and 0.01uF for even faster, but not a big a "bucket".

[Mac Walker]

This rule, 0.1 uF from power to ground, mainly applies to logic chips, does it not?

The purpose was to prevent noise on the power bus from triggering a clock cycle, in a chip that would relay on clock pulses.

Would apply to an LFO or a microcontroller, or a PT2399......but not so much an op amp?

[R.G.]

This rule, 0.1 uF from power to ground, mainly applies to logic chips, does it not?

The purpose was to prevent noise on the power bus from triggering a clock cycle, in a chip that would relay on clock pulses.

Would apply to an LFO or a microcontroller, or a PT2399......but not so much an op amp?

National Semiconductor literature from the time indicates that a 10uF paralleled with a 0.1uF per opamp IC was needed. The issue with opamps was not so much that a clock cycle would be triggered, but that the accumulated inudctance and resistance from the decoupling cap would lead to high supply impedance and possibly oscillation in the ICs - which amount to a gHz range transistor array. At quite-high frequencies, even an inch of wire to the decoupling caps amounted to enough distributed inductance to make things go off the rails.

[duck_arse]

you can use a vero layout on perfboard, if you can be bothered running all the traces needed.

I've never used perf.

I may just have to invest in some veroboard.  Why have you never used it?  Just don't like it?

when the boss had me making prototypes back when 64K bits ruled, and dinosaurs etc, it was only vero in the cupboard. I still hate using vero to this very day, but it has always been easier to hand than perf, and I don't have a pcb setup, so that's wot I use.

[Thecomedian]

Layout tips:
1. All wires and copper traces are really just low value resistors.
2. As a result, keep all signal wires as short and direct as possible and practical.
3. Make signal flow from input through the circuit as short and direct as possible.
4. To the greatest extent possible, keep all the components for one section of the circuit (i.e., amplifier or opamp section, or IC ) as close to the active parts in that section as you can. Resistors that connect to an IC, for instance, should be right by the IC unless there is a good reason why they must not be.
5. Bypass capacitors between power and ground may not be shown on schematics, but they are always needed. Use 0.1uF ceramic caps between power and ground pins as close to IC leads as you can put them. Yes, even for tested circuits. This can help (although not fully compensate for) otherwise poor layout.

Have you seen this before, R.G.?