Calculating negative feedback capacitor value

[thelonious]

I'm playing with a fairly standard JFET boost circuit, like this one from Muzique.com:


I'm messing around with negative feedback arrangements like adding a cap and resistor in series from drain to gate. Why? I don't know, for kicks. I've noticed that if I use a really big capacitor, like 220u, it will mess up the bias of the JFET, probably because it's charging through the drain resistor (or maybe the cap was leaky?).

My question is: how do I calculate the value of the cap needed? I know how to use Fc=1/(2πRC), but that doesn't do me much good if I don't know how to find R in this circuit. So... what thing, or combination of things, is R here? Is there a rule of thumb for determining which resistances/impedances are in play in an arrangement like this?

[R.G.]

I'm messing around with negative feedback arrangements like adding a cap and resistor in series from drain to gate. Why? I don't know, for kicks. I've noticed that if I use a really big capacitor, like 220u, it will mess up the bias of the JFET, probably because it's charging through the drain resistor (or maybe the cap was leaky?).

Really big caps are almost by definition electrolytic, and have a large - and variable - leakage. In fact, JFETs are or were used as front ends in leakage detectors. Let us know if any NON-electro caps show this problem.

My question is: how do I calculate the value of the cap needed? I know how to use Fc=1/(2πRC), but that doesn't do me much good if I don't know how to find R in this circuit. So... what thing, or combination of things, is R here? Is there a rule of thumb for determining which resistances/impedances are in play in an arrangement like this?

There is an unseen resistor - the resistance (= source impedance) of the signal source. Actually, there's an unknown one loading the output too, but that's not where your problem is.

But the real issue is that you have to know what frequencies you want to pass. If have some Rf and Cf in series (yep, I'm going to launch in to equations), then the capacitor impedance is equal to the feedback resistor at a frequency F = 1/(2*pi*R*C). At frequencies above that, the capacitor has less and less to do with whatever happens because its impedance drops well below the resistance value. So the JFET behaves as though it has just Rf for feedback, but DC is blocked.

Note that the opposite effect is happening on the source, where the source resistor and cap are in parallel. At frequencies much above F = 1/(2*pi*Rs*Cs), the cap acts like a "short" to ground, so the gain of the JFET increases from Rd/Rs at DC to yfs*Rd at frequencies well above that.

The feedback resistor Rf is a load on the drain of the JFET, and if it's much less than 10X the drain resistor, it's a significant load that affects the AC gain of the JFET as though it were a load on the drain alone.

The feedback resistor changes the input impedance of the JFET. At frequencies above where the feedback cap is not significant, the feedback resistor looks like a load to ground from the gate to the incoming signal. This loading is multiplied by the voltage gain, so it's Rf/G. The gain G is Rd/Rs below the source resistor/cap turnover, and changes to Yfs*Rd above it, so the loading of the Rf increases with both the gain increase/step from the source capacitor and the turnover frequency of the feedback Rf/Cf.

Once you have that all sussed out, you get to where the source resistor matters. The source resistor sees a load of 1M in parallel with Rf/G at any frequency. It also sees a feedback amplifier with that input impedance and a gain which approaches Rf/(source impedance) according to the classical feedback equations. Basically, as long as the AC gain of the JFET exceeds 10x the ratio of Rf and Rs, the gain is Rf/Rsource. If the open loop gain is not very much larger than Rf/Rs, the closed loop gain only approaches Rf/Rsource.

[PRR]

> cap and resistor in series from drain to gate.
> a really big capacitor, like 220u

What R.G. said about leakage.

> mess up the bias of the JFET

A CYI spec for electrolytic leakage is 1uA per uFd. At 220uFd, 220uA leakage. 220uA in 1Meg is 220 Volts!! OK, there's probably <9V available. And 1uA/uFd is very worst-case; I would expect far less. But even 100 times less, 2V, will still mess-up the JFET bias.


______________
Caveman thinking: 220uFd is under 100 ohms all across the audio band. The FET and other resistances are 1K or more. What will probably happen is that input goes THROUGH the 220u cap, NOT through the FET, which is just a drag on the input.

> from drain to gate.

Drain-Gate feedback is Miller Effect. The signal source sees an effective impedance of the feedback network, DIVIDED BY the gain of the amplifier. If you connect 100K (with a blocking cap) D-G, and FET gain is 30, then the signal source sees _3K_. This is super-low by guitar-cord standards. Results will depend a LOT on what is driving it. An over-wound pickup? A chip-based effect pedal?

Go ahead and play. Might be good to have a signal generator and audio voltmeter too. But in general D-G feedback is not a great tool for input stages in hi-Z work.

You may also want to review the literature on Inverting Opamp connections. This is the same thing, except Rin is some unknown quantity presented to your "In" point, and the JFET's gain can't be assumed "infinite" as is often done with opamps.

[thelonious]

A CYI spec for electrolytic leakage is 1uA per uFd. At 220uFd, 220uA leakage. 220uA in 1Meg is 220 Volts!! OK, there's probably <9V available. And 1uA/uFd is very worst-case; I would expect far less. But even 100 times less, 2V, will still mess-up the JFET bias.

Yikes. I had no idea they could leak that much and be within spec. Well, that would explain it!

The feedback resistor changes the input impedance of the JFET. At frequencies above where the feedback cap is not significant, the feedback resistor looks like a load to ground from the gate to the incoming signal. This loading is multiplied by the voltage gain, so it's Rf/G.

Drain-Gate feedback is Miller Effect. The signal source sees an effective impedance of the feedback network, DIVIDED BY the gain of the amplifier. If you connect 100K (with a blocking cap) D-G, and FET gain is 30, then the signal source sees _3K_. This is super-low by guitar-cord standards. Results will depend a LOT on what is driving it. An over-wound pickup? A chip-based effect pedal?

Ah. One of the things I was wondering about was if I could make a switchable buffer/booster with a variable Rf pot as the volume control, and have the bypass switch short the pot to apply heavy feedback for unity gain/buffered mode. But it sounds like that definitely wouldn't work, then, given the variation in source impedances and the Miller effect. I had been thinking of this kind of like opamp feedback loop---if you want unity gain you can get it by applying lots of feedback. But it actually sounds like it works more like tube plate-grid feedback?

R.G.: When I was reading more about what range of source impedance to expect and how it would interact with the JFET, I came across this reeally old thread:

Then there's the issue of loading. A pickup's internal impedance is primarily the resistance of the winding wire at DC, maybe 5K to 10K ohms, plus the inductance of the coil. So if you put a low resistance across the output, maybe 10K, the signal is divided across the pickup's internal impedance and the external load. If you put a high impedance across the output, the high impedance will let very little current flow out of the pickup, and so all of the pickup's voltage appears at the high impedance, very little is lost to the internal impedance of the pickup itself.

So a high impedance input on a buffer lets essentially no current flow into the buffer - that preserves all of the signal voltage to be amplified by the buffer since the buffer does not load down whatever drives its input. And that is the whole point of a buffer - it makes life easy on a signal source like a guitar, and provides the muscle to drive loads because buffers normally have low output impedances, so they can move a lot of current on their outputs.
[...]
A buffer only sips the tiniest amount of signal current, letting almost all of the signal voltage appear at the buffer input.

I'm used to dealing with AC current in reference to house power, transformers, etc., but I haven't thought much about how it applies to signals, impedance, and loading. Thanks to you both for the informative replies. Got some new things to chew on now...