18 volts, compression, headroom and transients.

[Groovenut]

Well, my main point is that if your input signal is larger with a higher supply voltage, then you WILL clip the next stage sooner than with a lower supply voltage, due to the fact that Vp is fixed for the JFET.

Groovenut - that seems to confirm what we've been saying, but it would be a lot easier to see subtle differences if the images were somehow normalized and overlaid on one another..

Fixed the image with an overlayed version

[PRR]

> you said Idss it kind of concerns me.  This says that the transistor will only ever pass some maximum amount of current.  That means that its minimum reffective resistance depends on the supply voltage.

Transistor does not "see" supply voltage directly. It sees supply THROUGH a resistor.

For any semi-sane design, Rd will be >Vd/Idss

(Anything lower leaves both gain and max-output on the table.)

Transistor will be able to pull-down to very low voltage (roughly Vp).

[Frank_NH]

Thanks Groovenut!  I have a spreadsheet which does the calculations for a common source JFET stage.  You provide Idss and Vp and it calculates gain, voltages, currents.  Pretty much, the gain scales with the supply voltage.  And with a large source bypass cap, the gain will about double.

I'm assuming your clipped waveform is due to your 2N5457's Vp being ~ 1.5V - 2V?

[Groovenut]

Thanks Groovenut!  I have a spreadsheet which does the calculations for a common source JFET stage.  You provide Idss and Vp and it calculates gain, voltages, currents.  Pretty much, the gain scales with the supply voltage.  And with a large source bypass cap, the gain will about double.

I'm assuming your clipped waveform is due to your 2N5457's Vp being ~ 1.5V - 2V?

Yes. I just took the input signal up to where it started clipping so I could center bias the fet, then left it there to show the input signal (clipping) scales with the voltage and gain when the bias was adjusted.