Transistor buffer with x2 gain *and* high input impedance?

Started by ElectricDruid, September 20, 2016, 10:54:53 AM

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R.G.

Just to gather a few things up:
- If it's a PIC family part, yes, the source impedance needs to be under 10K to meet its sampling rate and accuracy specs.
- Using a shunt diode stack for protection is a good idea, not least because it makes signals sound "organically" limited, not splat-limited like most overdriven A-Ds. The PICs are tough, so long as the current in any pin is less than 25ma, but shunt diode "clippers" will make overdrive sound much more acceptable.
- 32kHz sampling is going to need significant filtering on the front end, probably no higher than 10kHz and three-pole. Guitar gets there OK by itself, but when a guitar signal is passed through pedalboards, you get harmonics that go higher.
- 12 bits is OK-ish, although a little grainy sounding. There were a couple of early digital delays that used 12 bits. Quantization noise creeps in unless you do some noise shaping and filtering.
R.G.

In response to the questions in the forum - PCB Layout for Musical Effects is available from The Book Patch. Search "PCB Layout" and it ought to appear.

PRR

> I recall a max Z(in) of 10k
> source impedance needs to be under 10K


Well, OK.

A simple collector-loaded BJT stage, Zout is Rc. Set Rc=10K.

Gain of 2 (still doubt this) implies Re + hie of 5K.

Raw Zin is hFE*5K. For hFE>500 we get over 2 Meg.

Simple 4-resistor bias, for good hFE stability we would like the lower Rb say > 20 times Re, or 100K. A bit low. Collector feedback can use a far higher resistor, say 5Meg. Miller Effect reflects a lower input Z, but gain=2 only ~2Meg. So we have a 2meg||2Meg= 1Meg input.



With 0.01u input cap, -3dB happens at 13Hz, implying Zin significantly over 1meg.

With 5V supply, almost 3.3V p-p out, with ~~5% THD lightly overdriven.

As the absolute max output current is 5V/4.7K or 1mA, protection is not needed unless there is a silly latch-up. Since it will be AC coupled, actual signal current will be a small fraction of a mA, which seems less-likely to turn a pin-input into a latched SCR.

That 100pFd load gives -3dB like 140KHz, so a fatter cap could be used to roll-off the supersonics and absorb ADC glitching.
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