Jfet Cut-Off etc

Started by sbirkenstock, January 16, 2017, 02:50:59 AM

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Eb7+9

#20
Quote from: R.G. on January 22, 2017, 11:06:53 AM

... yes, I know that Vp and Vgsoff are not technically the same, just very close to one another in value.


deep ...


actually, they "are" technically the same thing ...

Vp is defined by Vgs(off) directly as Vp = -Vgs(off) ...

ie., the same thing in magnitude

|Vp| =|Vgs(off)|



https://www.quora.com/What-is-the-difference-between-a-pinch-off-voltage-and-a-Vgs-off-in-a-JFET

https://www.physicsforums.com/threads/confusion-regarding-pinch-off-voltage-in-a-jfet.734222/

what do you know ...

EBK

Quote from: Eb7+9 on January 23, 2017, 02:23:22 AM
Vp is defined by Vgs(off) directly as Vp = -Vgs(off) ...

ie., the same thing in magnitude

|Vp| =|Vgs(off)|
which is another way of saying they are not technically the same.  :icon_razz:
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Technical difficulties.  Please stand by.

R.G.

And today we have the 160th last time J.C. will bring it up, as predicted about a day later.

J.C., just drop it will you? It's very tiring of you.
R.G.

In response to the questions in the forum - PCB Layout for Musical Effects is available from The Book Patch. Search "PCB Layout" and it ought to appear.

Eb7+9

#23
funny EBK ... I knew someone would pull a technicality on me

:icon_biggrin:

for those interested in further learning/discussing ...

I stand by everything I said so far, ... here's a synopsis of the discussion

---

as Rob pointed out the Keen test forces a roughly constant 400uA thru a jFET
and the tester measures Vgs ... simple, ... nothing more

producing a single {voltage,current} data pair somewhere inside the operating range of the DUT  ...
(devices with Idss value lying below 400uA be damned)

that much we can accept as fact here

I'll say it again ... the Keen test does not,  and cannot, infer Vgs(off) in any way ...
much less Vp ... its numerical inverse

consequently, I see it as a misleading way to select devices for phasor circuits /...
ie., it doesn't come with any real guarantee of matching the chief parameter relevant in VCR applications

(the subject of this thread)

http://www.vishay.com/docs/70598/70598.pdf

in fact, in so doing, this "non-zero operating point test" lumps together the mutually independent Vgs(off) and Idss specs .. and it is understood that these two constants act to "define" both sets of DC transfer curves for any given jFET device ... they acts as anchor points // and their graphical definitions are clearly made in the theory ...

so, here's the crux ...

some peeps make the mistake of believing there's a "strictly monotonic" relationship between Vgs(off) and Idss
or that the quadratic Source function is fixed in form (it isn't) ... I strongly suspect this is the assumption made in the Keen test, or one like it ... at least that's what people do with bipolar transistors, I can understand the temptation ... I guess

this is one aspect that differentiates jFET (and MOSFET) transistor analysis from their bipolar counterpart // ...

---

the next exercise will be to take devices that have been "correctly" characterized
and make them go thru the Keen test jig and show how locus' of equivalences lump
devices together despite having diverging Vgs(off) values ... (just like Rob Strand says he did)

this is nothing new, it was mention in Sebastian's "Greatly Improved jFET Matcher" thread where he describes exactly the same thing I'm talking about here, except I'm taking it one further and seek to describe the false-positive "equivalence class" aspect of Keen's test jig ...

http://www.diystompboxes.com/smfforum/index.php?topic=29513.msg200858#msg200858

it's the why part in the math I'm interested in ...

Rob Strand reported a false match in about 10% of cases in his two-pass testing ... very note worthy results

http://www.diystompboxes.com/smfforum/index.php?topic=115878.msg1071305#msg1071305

a proper testing/matching regime comes with a 100% success
not a statistical (random) one ... with a 10% degree of "false pass" error

clearly, this cannot qualify as a testing method

---

I can see why Keen would want me to quit at this point ...
but I really think there's an opportunity to fully answer a couple of burning questions

otherwise, what's the point talking about anything ... it's what forums are for ;)

regardless of how tired or annoyed Keen might seem at this point
I'm looking forward to seeing "Keen lumps" emerge from my jFET data collection ...
should make an interesting graph for sure

and while I'm at it, I might even take the trouble of deriving the equation/relationship that certainly must exist between Vgs(off) and Idss value pairs lying within these "equivalence" lumps ...

and lastly,

to get an idea of how bad the divergence can actually get // ie., to see how far these locus' groupings might extend "across" my data sets ... in particular, to see how divergent the spread of Vgs(off) values can be within these "false positive" lumpings ... hopefully laying to rest the whole "Keen jig" accuracy question

---

thank you to all the contributors

merlinb

#24
Quote from: Eb7+9 on January 24, 2017, 05:21:42 AM
I'll say it again ... the Keen test does not,  and cannot, infer Vgs(off) in any way ...
much less Vp ... its numerical inverse
Hmm, whilst I agree that Vgs(off) or Vp and Idss are both more useful and simpler to measure than RGs arbitrary Vgs choice, I don't think he ever claimed to be measuring Vp. On his page it simply says:

"The opamp's job is to compare the two voltages and make the voltage on the JFET gate just right so it looks like a 10K resistor (same voltage and current) in this setup. There's nothing magic about the 10K value for Rset, it's just a convenient value that's going to be about where a lot of our circuits will wind up."

So really he 'matching' JFETS to give a 'useful' effective resistance of 10k at a particular Vgk. That's all. Exactly how they deviate from 10k as your LFO swings up and down will of course not be matched, but as long as you're bobbing around the useful figure of 10k this probably doesn't matter too much. I do think RG was overthinking it though (sorry!  :icon_redface:).

Eb7+9

#25
you think he's over thinking ... I think he's under thinking
same thing, 180 ...

thanks for pointing out the Vp thing ... I went back and re-read this

Quote from: R.G. on January 21, 2017, 09:11:15 AM

Nota bene - what's actually being measured in the "most of the JFET testers floating around this forum" is Vp


I thought it was referring to his jig ...

if I got it wrong, my bad // sorry

now, don't get me wrong ... I can admire someone who'll go out on a limb and try to be original
but still, the rest of it stands - the analysis part

like I said before, the Keen test ON ITS OWN does no better that what we'd have if we merely biased a jFET with a Source resistor

it is in general known that two sufficiently separated data test points are needed to extract jFET device characteristics accurately and completely ... can't do it with just one ...

the Vgs(off) or Vp test and Idss tests give two data point pairs that in the extreme ranges of the data
other than that there's no special magic quality to these (Vgs(off),0) (0,Idss) points as far as characterizing the devices ... it's just that these values play special roles in many circuits, and aren't chosen only for their looks ... it's useful to know them, even becoming the starting point in some designs

---

see here's the thing about Keen's "forced current method" ...

let's say he was a little bit more careful with Idss to begin with (easy diode test)
all he'd have to do then is change the test-current level and repeat the test a second time

NOW, we have a completely different game going on ...

say that we knew in advance that Idss was less than 600uA on a group of test devices
and we chose to do the test at 500uA and then 50uA
(for devices with higher or lower Idss specs, we would adjust test currents accordingly)

THEN we'd have ourselves a proper basis to claim matching with ...
we'd then be left with Vgs(500u) Vgs(50uA) data pairs

any two devices for whom these pairs equate would then be deemed matched
that's the deal right there

in the std. Keen test where only one such voltage is extracted
there is by necessity a real chance for mismatch in the true sense of the word

---

the whole 10k resistance thing is completely incorrect by the way ...
in fact it's so obviously wrong that I won't go into it ...

in VCR/audio applications we are interested in AC resistance
in the Keen jig this is confounded with DC conditions

... like I said, all this circuit does is bias a jFET, albeit with a controlled current
(which would be useful if a second test were performed)

which it isn't ... but now, maybe it will // who knows ...
just expect much less devices to now "match" under these 2-data-point conditions

but still we will not be any closer to having any real idea of Vgs(off) for that device
(other than running heavy math routines to derive them)

yawn ...

which is why we might as well shoot for that Vgs(off) test right off the bat instead

plus it's trivial to set up ... a DMM and 9volt battery will do for most of our audio jFET's

it certainly would help in advance to "know" where the bias limits of our devices lie
either in the matched case or, as I showed with my Paradigm Shifter, in the un-matched case

skip all the guesswork in building phasors etc etc ...

R.G.

Well, J.C., we are treated to #'s 161 and 162 on the same day.

Merlin, you're feeding the troll. He will never go a way and stop this as long as someone is responding in even a neutral way to him.

No amount of reason, pointing out the utility of a quick and dirty test, how well it's worked for how many people for how long, etc, will ever get him off his screaming fits that "butbutbut it's not PERFECTLY ACCURATE  and doesn't measure EXACTLY THE RIGHT THING!!"

J.C. seems to be mentally committed to the pedantics of this, and can't leave it alone.

I expect 163, 164, and 165 in short order. Come on J.C. don't fail me now.  :icon_lol:
R.G.

In response to the questions in the forum - PCB Layout for Musical Effects is available from The Book Patch. Search "PCB Layout" and it ought to appear.