Terminating unused invertor sections

[Mark Hammer]

The general recommendation for unused sections of a hex invertor is to tie each unused invertor input to a steady voltage.  When I look around at the various schematics I have, sometimes I see the inputs tied to ground, and sometimes I see them tied to V+. 

Is there a difference between the two alternatives, either in terms of the resulting noise, or in terms of the current draw?  I know the old EHX Hot Tubes tied unused inputs high (to V+), but I also know that, despite CMOS chips apparently drawing little current, the Hot Tubes felt compelled to use an AC power source, without battery option.

Given that these are invertors, tying the input high means the output is always low, which I assume implies less noise.  On the other hand, grounding the input means the output is high.  Are there implications for current draw?  Inquiring minds want to know.

[anotherjim]

I don't think there are any noise implications for either. Certainly will be noise if the inputs are floating.

We may prefer inputs grounded because there seems less risk of accidental shorts compared to running the +supply around.

[Mark Hammer]

Makes sense, but I still have to wonder what motivates the connection to V+.  Coin flips don't strike me as the basis for electronic design, so the V+ folks must have had something in mind that the ground people didn't.

[Fender3D]

Unused invertors won't make "noise" per se, since they're not connected to audio path, they usually "tune" with the frequency(es) of others (used) invertors, thus auto-oscillating or, with the help of stray capacitances, simply auto-oscillate.
Tying them at a steady voltage will block any auto-oscillation.
Tying them at +V or GND is usually a matter of PCB layout.

[amptramp]

One of the things I experimented with when working on remote sensing / infrared scanning equipment was making an amplifier using CMOS inverters cooled to the temperature of liquid nitrogen, 77 Kelvin.  With the input either high or low, the current drain was extremely small.  With the input biased at the midpoint, the current per amplifier was 8 mA.  The results?  Cryogenic CMOS inverters could not achieve the noise performance of good amplifiers operating at room temperature and every once in a while, there would be a large transient which we assumed was tectonic breakup of the silicon die at low temperatures.  We abandoned that one.

[greaser_au]

During my diploma course  it was explained that TTL/LSTTL with totem-pole outputs used to suffer from current spikes as the output state changed, because both devices in the output stage are passing current at some point during transition. Tying input to ground or pulling up with a resistor prevented a floating state that could land the totem-pole sitting in the 'linear region' and drawing a lot of current.

It was not unusual to see a half-unused  'LS04 (hex inverter) with the output of one gate joined to the input of the next (adjacent pins) down one side...

Thinking about it (not sure if it's a wild flight of fancy or something I read a long time ago) I could imagine in the TTL days with densely populated designs, some power savings could be made by taking the option with the most internal transistors biased off? 

Time to dig out the old databooks - some of the manufacturers used to include best-practice notes in the family databook (something the individual data sheets often don't provide).

david

[R.G.]

The output of a CMOS gate has one P-channel transistor to V+, and an N-channel to V-/ground. When the output is at a fixed logic state, whether + (1) or - (0), One output is fully on ( = a resistor to the power supply it connects to) and the other is fully off, effectively an open circuit.

If there is no output load, it does not matter which state the gate is set to. There is no path for current from V+ to V-, so no current flows. In the real world, only immeasurably small currents flow. So if there is no load on the output pin, it does not matter at all which state the input sets the pin to. If there is any loading on the output pin, the input state and resulting output state matters a lot, of course.

The input of a CMOS gate must always be set to either V+ or V-. The input of a CMOS gate is a sheet of glass 20 volts thick. Immeasurably small currents (to us) flow through the glass/oxide layer. It is effectively an open circuit. The input currents in active CMOS logic are usually modeled as a pure capacitance. The DC portion of curent into or out of a CMOS gate is as close to 0 as anything in the pedal world. So it does not matter to the gate whether the input is tied to V+ or V-; no current flows in the input.

Here are the caveats. Do NOT hold the inputs in the no-man's land in the middle of the logic swing unless you know what you're doing. This sets both the P-channel and N-channel devices on at the same time, and eats a relatively huge cross-conduction current. This is OK under the limited conditions of a linear biased, unbuffered stage as in the CMOS inverter distortion/amplifier things, but things can get out of hand with buffered gates and parasitics on the PCB. Do NOT leave an input open. It can and often will pick up stray power line voltage and RF stations from the air and wiggle the output around.

Each logic family has different issues with where the output is left as a fixed condition. Yes, TTL had different output stages, and different special conditions. To today's logic designers, TTl seems as quaint as RTL, relay and diode logic.

There really is no primary reason to pick unused inputs and outputs tied high or low. The secondary reasons have it all: Nearness to another pin, or a nearby ground plane, that kind of thing for layout ease. Smart designers of first-protos PCBs will make it easy to cut the inputs loose to use them in patching the logic. 'Course, I never had that problem.    

[greaser_au]

To today's logic designers, TTl seems as quaint as RTL, relay and diode logic.

It really does seem to be that way.... Need a spare inverter, just use a PIC/ATmega, it would even have less pins!   But seriously, these days an FPGA or microcontroller would be the 'right way' to create something (unless you have a drawer full of 74/4000 and some time to spend).  It's a little sad, because the budding engineer really misses out on the hands-on 1s and 0s, not gaining experience in (read: "trip over, and waste hours and hours on finding out the hard way") practical aspects like inadequate decoupling,  fan-out limits, race conditions - and discovering where that no-man's land between 1 & 0 is...

There really is no primary reason to pick unused inputs and outputs tied high or low. The secondary reasons have it all: Nearness to another pin, or a nearby ground plane, that kind of thing for layout ease. Smart designers of first-protos PCBs will make it easy to cut the inputs loose to use them in patching the logic. 'Course, I never had that problem.   

I once had to cut a (thankfully) thermally relieved sub-surface ground plane connection out of a batch of PCBs, I did this with a 0.2mm dental ball mill under a microscope equipped with a polarised light ring.  I would *not* be able to do that now.  The alternative would have been to drill the thru-plating out and sleeve the hole

david

[anotherjim]

If the designer left the inverters nearest the +V pin unused, then it may just have been layout ease that chose + tied inputs.

Designer might believe that input tied low so the outputs are high. Then if there was an accidental short to chassis then the chip may be damaged. To put it another way, if input is tied to +v, then fault current bypass the chip, if input tied low, then fault current passes through the chip. There's some sense in that, except there will usually be just as much chance of that happening with an output of a used output that is meant to be high.

I could never find out why unused TTL inputs tied high should be done via a pull up resistor rather than direct link. TTL logic boards often had 10k or 4k7 resistor packs providing the pull-up resistors. I've been told it was a noise issue, but didn't get an explanation for it. High connection is common with TTL because control inputs like Set & Reset are active when Low - the opposite of 4000 series CMOS.

[PRR]

> why unused TTL inputs tied high should be done via a pull up resistor rather than direct link.

Many commercial designers just linked.

Apparently some MIL-spec required a resistor, so you could not have "infinite" current in an unexpected condition (supply over-voltage, transient or ongoing). The input emitter junction will break-down at 7V reverse bias. Yes, this would be 12V supply! Stuff happens, or caution in abundance. With resistor, the input can stand well over 50V.