Another boring FET bias thread (azabache)

[Frank_NH]

Here's my take...

The input limits for an n-channel JFET in a common source amp configuration (with self bias such that the gate voltage is biased at 0V) can be figured out as follows.  We assume that our bias point is such that we have current flowing through the JFET, and that the drain and source currents Id, Is are equal, and that the gate voltage Vg is less than the source voltage Vs.

Let's consider the case where our gate voltage (input signal) Vg is going down.  Then Vgs = Vg - Vs is becoming more negative and the JFET current (Id = Is) starts to drop.  But if the current is dropping, so is Vs for a fix source resistance Rs by Ohm law.  Eventually, Vgs --> Vg(off) = -Vp (the cutoff voltage), and all current ceases: Id = Is = 0.  Notice that at the same time Vd --> Vdd (source voltage) and when the current is off, Vd = Vdd, which represents an upper limit for Vd.  Since at this point Vs = 0, it follows that Vg = Vgs = -Vp.  Making the input (gate) voltage any lower will not change the output.  Thus, this represents the lower limit of the input voltage.

Now consider the case where the gate voltage increases.  As this occurs, Vgs starts getting smaller, and the current Id = Is increases.  As the current increases, so does Vs (since the Rs is fixed).  Eventually, though, we reach the point where Vgs = 0, or Vg = Vs.  Here, the JFET is flowing it's maximum current, Idss.  Knowing Rs, we can calculate Vs = Idss*Rs = Vg.  So the maximum Vg we can handle depends on Rs and Idss.  Of course, the whole point of operating a JFET as an amplifier is to bias the JFET so we don't hit the extremes;  however, if the point of your application is to clip the output signal like an overdriven tube, then having a smaller magnitude Vp (Vgs(off)) - like a J201 - is an advantage.