### Author Topic: Help with 10:1 design rule  (Read 512 times)

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#### rockhorst

##### Help with 10:1 design rule
« on: March 07, 2018, 06:01:18 AM »
I'm designing a circuit and am trying to keep in line with that famous 10:1 design rule: keep impedance/resistance of a circuit stage about 10 times smaller than the stage following it. I've tried to do that roughly in the circuit below. The circuit starts with the output from a buffer (which is not shown), goes through two passive filters and then splits into two level controls followed by a new buffer. One of the buffers is non-inverting, the other inverting. This has to do with the rest of the circuit and needs to stay in tact. I'm assuming the two output buffers to drive stages of about 1M impedance.

I'm not entirely sure about my application of the rule and Thevenin equivalent circuits. I would appreciate a few extra eyes.

My reasoning, going a little fast and dirty with the math (probably flawed):
The Treble pot sees 1k2 parallel with 22k (max), which together is about 1k -> use a 10k pot.
The following Level pots see each other and the filter circuit in parallel. The filter circuit in DC looks like about 5k -> I select 50k pots for the levels.
Looking back from beyond the Level pots the circuit looks like about 25k. I could bump up R4/R5 and R7, but that's probably not needed.
R6 and R8 set my output impedance at 100k. 10k would work well also, but increases the size of the capacitor which is not handy from the perspective of board real estate. 47k might be a nice trade off there (as a 100n cap is the same size as a 47n).

Any thoughts?
« Last Edit: March 07, 2018, 06:03:45 AM by rockhorst »
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#### antonis

##### Re: Help with 10:1 design rule
« Reply #1 on: March 07, 2018, 06:52:33 AM »
Your calculations confused me a bit so I'm not able to follow them..

If you look at it from the end to start, ignoring caps impedances (short-circuit) and setting all pots to middle position, R4 is set in parallel with half Level1 pot - the other half of Level1 pot set in series with the previous combination..
(i.e. (50k//120k) + 25k = approximately 45k, named Rup..)
Same for Level2 & R7 results in Rdown of also 45k - to make both resistances presicely equal, make R7=120k (or R4/R5=100k)
So, at splitting point (Treble pot middle lug) the equivalnet resistance going to AC GND is 22k5 (Rup//Rdown)
That point "sees" 22k5 in parallel with [half Treble pot resistance + R3 = 17k] resulting in 9k68..
Input voltage divider point (C2 right leg & R2 upper leg) "sees" [R2 + half Bass pot = 17k] in parallel with [half Treble pot + 9k68 = 14k68] resulting in 7k88..
So, buffer output signal is attenuated by (R1 X 7k88)/(R1 + 7k88) = 0.868

Maybe my maths aren't correct but you get the point..

#### rockhorst

##### Re: Help with 10:1 design rule
« Reply #2 on: March 07, 2018, 08:28:37 AM »
Thanks for the input Antonis. You're math is different from mine, attenuation is in the same ball park, though a bit worse. I didn't take R4 and R7 into account. Also I think it's most sensible to use the full 10k of the Bass pot as a worst case scenario. R7 to 120k makes things nicely symmetrical.

I ran a simulation that exactly matches your calculation if I use 100k level pots (0.868 attenuation). With 50k level it's not far off (attenuation 0.847). That's a bit much for my taste. Halving R1 seems to be the fastest way to bump this up. I'll redo my own calculations later today, see if I can match yours.

Other suggestions for the circuit still appreciated. I tried to also scale the Treble and Bass pots in a proper way. Any ideas on that?
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#### antonis

##### Re: Help with 10:1 design rule
« Reply #3 on: March 07, 2018, 08:56:14 AM »
I still can't figure out your issue..

Do you notice some attenuation at high frequencies or what..??

#### rockhorst

##### Re: Help with 10:1 design rule
« Reply #4 on: March 07, 2018, 09:00:14 AM »
No, it's a theoretical exercise at the moment. Trying to minimize attenuation by choosing the right pot values, but there's no real problems with the circuit otherwise. The basic circuit is just fine, it's the split that got me a bit confused. R1 is used to smooth some clipping diodes to ground. I can move R1 to be parallel instead of series and all should be well.
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#### antonis

##### Re: Help with 10:1 design rule
« Reply #5 on: March 07, 2018, 11:53:40 AM »
R1 is used to smooth some clipping diodes to ground. I can move R1 to be parallel instead of series and all should be well.
In theory, they shouldn't be OK..

Due to diode absence on shematic, I presume their placement between R1 & C2..
If so, you can place R1 in series with diodes and this series combination in parallel with following circuit ..
(there isn't any sole capacitor to GND after C2 so you shouldn't have any buffer current limiting issue..)

BUT, you have then to consider R1+Diodes in parallel with 17k (according to my maths.. ) and the hidden buffer output impedance has to be equal or less than 1/10 times the new equivalent resistance of all these - BUT diodes aren't "linear" items AND R1 apparent low value dominates enough the following circuit so I think you're getting into theoretical exercise trouble..
(e.g if you consider diodes as AC short - even off-setting for 700mV - total equivalent resistance is less than 1k so a JFET buffer of transconductance lower than 10mS can't satisfy your 10:1 requirement..)
« Last Edit: March 07, 2018, 12:27:22 PM by antonis »

#### rockhorst

##### Re: Help with 10:1 design rule
« Reply #6 on: March 07, 2018, 12:45:27 PM »
I've redrawn the schematic starting from one of the opamp buffers and mirrored everything, pots half way (except bass: full). For simplicity lets also assume both opamps are non-inverting. All capacitors are replaced by short circuits. I get the following equivalent circuit then, if I didn't make any errors.

The discussion above boils down to this then: I don't know how to account for R1 in calculations, as it's not attached to ground. Please illuminate

Edit: I saw Antonis edited his post as I was writing mine. The hidden buffer is another opamp buffer or amplifier. It's all quite similar to amp/clipping part of a Marshall Guv'nor circuit. The diodes are LEDs, so about 1.3V drop.
« Last Edit: March 07, 2018, 12:49:44 PM by rockhorst »
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#### R.G.

##### Re: Help with 10:1 design rule
« Reply #7 on: March 07, 2018, 02:30:01 PM »
It's worthwhile remembering all the footnotes to that "rule".

1. It's a rule of thumb, not something that absolutely has to be followed, or a law of nature.
2. The intent of the rule is that if you follow it, you can largely ignore source and load impedances as causing overlapping, loading, lower volume, frequency losses, etc.

Buffers are things which let you isolate stages which can't easily have at least a 10:1 source to load mismatch. They generally have high input impedances and low output impedances. So they're there for when you can't get a 10:1 mismatch and not worry about it.

One good illustration is that unshown first buffer. It decouples you from the truly tough to deal with source impedance of a guitar pickup, and gives you a starting point in the impedance chain of "small impedance".

The problem with tone controls and input/output impedances is that for a fixed capacitor value, the rolloff corner frequency changes with both source and load impedances, so that in a variable resistor setup, the tone/frequency rolloff moves with the setting of the pot(s) unless the caps are simply so large that the pots don't matter - and that's never true in a filter setup like a treble control. So to get independence of your filter frequency from pot settings, you either use the 10:1 >>guideline<< or install buffers to make the frequencies independent of the pots, or live with the interactions.
R.G.

Quick IQ Test: If anyone in a governmental position suspected that YOU had top-secret information on YOUR computer, how many minutes would you remain outside a jail cell?

#### rockhorst

##### Re: Help with 10:1 design rule
« Reply #8 on: March 07, 2018, 02:59:38 PM »
So to get independence of your filter frequency from pot settings, you either use the 10:1 >>guideline<< or install buffers to make the frequencies independent of the pots, or live with the interactions.

Which is indeed what I'm trying to do and I think it sort of works out, except for some level attenuation. I'm just not entirely sure of my reasonong in a bigger circuit snippet as this. I have a tendency to want to match theory with 'works well enough in the real world' hoping R.G. or someone can help me through that part. I only just passed my EEE class in college and it's a long time ago.
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#### PRR

##### Re: Help with 10:1 design rule
« Reply #9 on: March 07, 2018, 06:43:12 PM »
> I don't know how to account for R1 in calculations, as it's not attached to ground.

So what IS it attached to? A buffer.

If it is a good buffer, it presents a way-low impedance version of its input.

Assume the input is "silent". (It often is.) "Silence" defined as "no variation from zero Volt reference, ground".

Now what is the difference between buffered silence and just ground? Nothing.

Here is a different analysis. Did you pass DC circuits? Replace buffer with a 1.0V dry cell. Replace all large caps with shorts. This gives the voltage everywhere for low frequencies. Now replace all small caps with shorts. This gives the high frequency voltages. "Large or small" has to be relative to the resistances: 1uFd is large for a 100K load but puny for an 8 Ohm load.

#### rockhorst

##### Re: Help with 10:1 design rule
« Reply #10 on: March 07, 2018, 07:19:39 PM »
Thanks PRR, that helped a lot I redid my calculations and arrive at the same thing Antonis had.

"Large or small" has to be relative to the resistances: 1uFd is large for a 100K load but puny for an 8 Ohm load.

Could explain this a little further? Are you basically referring to the RC-time? Or am I way off here.
D'oh...figured that one out.
« Last Edit: March 08, 2018, 05:28:34 AM by rockhorst »
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#### antonis

##### Re: Help with 10:1 design rule
« Reply #11 on: March 08, 2018, 07:54:52 AM »
I don't know how to account for R1 in calculations, as it's not attached to ground.
Honestly, I can get what's puzzling you..

Left side of R1 is connected to a buffer (which you may consider as a voltage source of way-low impedance, as Paur said..)
So, R1 appears in series with buffer's impedance & C2 and this series equivalent impedance forms a voltage divider with the equivalent impedance of whatever comes next to C2 - 'cause splitting to GNDs starts right after C2..)

Considering output impedance of a "good" buffer being less than 100R, say, R1 remarkably dominates buffer's "effectivenes"..
(e.g. Voltage drop across 10k load fed from 1V source of 100R internal (output in circuitry) impedance is 990mV.. - with R1 set in series, voltage drop is hardly 885mV..)

Or just confused you more..??

#### rockhorst

##### Re: Help with 10:1 design rule
« Reply #12 on: March 08, 2018, 02:37:58 PM »
Or just confused you more..??

No no, I follow You're saying this

The second opamp only 'sees' the voltage drop over REST and so the signal is attenuated.

I just realized (and maybe this is what R.G. was hinting at) that this discussion is about two different topics:
- minimizing interplay between controls
- level attenuation between buffer stages

If possible, I would like to explore #2 a little further. It ties in with some other questions I had so why not tackle those as well.

1. It seems that a bigger REST resistance or relatively smaller R! gives me the least signal attenuation. If often see it mentioned that the left opamp 'drives' R1 (and REST) and this should not be too low. Is that because of the internal impedance of (say) 100R you mentioned?

2. Adding diodes or LEDs to ground can upset things quite a bit. You mentioned that R1 in series to ground with the diodes would be a bad idea. We then have R1 and diodes // REST. What trouble will I get into with that?

3. The buffer/opamp first in a single supply circuit usually has a big resistor to bias voltage connected to its input to set up the bias. I've noticed that you can from there on string along consecutive opamp stages with no new bias resistor as long as no capacitors appear in the signal chain. I see this DC coupling for instance in the Mesa Throttle Box. Opamps are connected output to input directly or with a smallish load resistor between them (1 to 3 kOhm in the Throtlle Box), but no parallel resistor to ground/bias. Why does this work? Ideally opamp inputs draw no current, so how does the right opamp 'see' the signal coming from the left?

Sorry for stringing on questions, but this is all very informative for me

« Last Edit: March 08, 2018, 02:46:41 PM by rockhorst »
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#### antonis

##### Re: Help with 10:1 design rule
« Reply #13 on: March 09, 2018, 09:05:21 AM »
1. Not exactly..
REST is driven from whatever comes before it..
In your case this is amp out resistance in series with R1 (100R +1k2)
Considering amp out resistance negligible, REST is only driven from R1..
The less the value of R1 (or the high the value of REST) the less the attenuation..
You even may omit R1 in case of no amp output current restriction..
(not true in your second scheme with clipping LEDs..)

2. I indeed mentioned that but from impedance domination point of view..
You'll place R1 in parallel with REST (considering LEDs as shorts to GND) resulting in new REST = 1k138..

3. Intermediate bias resistors should be needed only in case of capacitively coupled amps (no DC pass hence no bias voltage on amps inputs..)
You may had notice that we refer on "Voltage" rather than "Current", at least on "ideal" situatuations..
(Voltage difference between two points can be established with or without Current flow but Current flow can't be established without Voltage difference - I don't underestimate your knowledge on electricity.. I'm just trying to clear things up..)
Signals travel through wires with no cost (no resistance hence no voltage drop) so there isn't any problem for a signal carring some voltage difference between itself and some other point to deliver this difference between amp input and the previously mentioned point - which voltage difference can do its job inside amp..

But now you've confused me 'cause if you can't get it for signal case you should also can't get it for bias case..
(if amp should need some current to work it should stand for both signal & bias cases..)

#### rockhorst

##### Re: Help with 10:1 design rule
« Reply #14 on: March 09, 2018, 09:29:13 AM »
You'll place R1 in parallel with REST (considering LEDs as shorts to GND) resulting in new REST = 1k138..

But now you've confused me 'cause if you can't get it for signal case you should also can't get it for bias case..
(if amp should need some current to work it should stand for both signal & bias cases..)

Gut felling says REST resistance becoming relatively low would be not ideal, but inside a circuit, without long signal traces, it shouldn't really be a lot of a problem? If someone has a good link that explains how (modern) opamps like to drive stuff, much appreciated.

Your second remark: I'm not to sure what you're saying, but that's a language thing I think. But thanks a lot for thinking along great help.

As for my knowledge of electricity: I teach it at the high school level, but more from a physics point of view than engineering. Which sometimes hinders me a bit. It's no problem for me thinking of voltages/potential differences without currents flowing, but part of me still wants to reference it to ground or bias. On the other hand, if the job of the opamp (as a black box) is to keep the + and - terminals the same, the signal at the input is just copied to the output nicely. Is it automatically referenced by the power rails?
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#### antonis

##### Re: Help with 10:1 design rule
« Reply #15 on: March 09, 2018, 11:42:20 AM »
Gut felling says REST resistance becoming relatively low would be not ideal, but inside a circuit, without long signal traces, it shouldn't really be a lot of a problem?
Let's try once more..

REST value doesn't mind at all for amp input current feeding but DOES mind a lot for voltage setting..
Amp input "sees" REST/(REST + R1) times signal voltage before R1...
(after all, REST simply forms a humble voltage divider with R1..)

Your second remark: I'm not to sure what you're saying, but that's a language thing I think.
It's indeed my English language limited skills..
I was trying to tell you that you should have the same query for bias as for signal..
(with no input current, amps couldn't "see" bias voltage as well as they couldn't "see" signal..)

It's no problem for me thinking of voltages/potential differences without currents flowing, but part of me still wants to reference it to ground or bias.
That's the "other" point mentioned in my previous post..
<a signal carring some voltage difference between itself and some other point>