I haven't a clue where I downloaded it from so I can't point you to it.
I think it was from the CAG (Cloned Analogue Gear) site.
I am wondering if anyone has successfully completed this phaser. There is at least one error on the PCB layout with the bias trim pot connected to the wrong place.
I've never build the whole thing on the PCB but I've build my own verions with similar blocks - the idea does work. I seem to remember the article, or a errata note from the magazine, mentioning the pot isn't as shown on the schematic but it should still work (I think the pot on the PCB went between +V and gnd, instead of Vref and gnd).
I've fixed this on both boards but I continue to get loud static no matter where the trimpot is adjusted.
So you aren't even getting clean signal through? It sounds like the whole show if off the air. You should at least be getting clean signal. Try temprarily lifting the resistor between the all-pass stages and the transistor stage - I think it's 5.6k. If don't get clean signal now it's time to debug the clean path. Measure the voltages on the all the opamp outputs and the transistor pins. From that you should be a able to see where things are pooping out.
Can someone explain how this works?
It's clearer to say the inverters are being used as individual N-channel MOSFETS - the weird connections are all about disabling the P-channel devices and pilfering the N-channels out fo the inverter. Once you see that yu will find it isn't much different to a JFET design. JFETs and MOSFETs can both operate as variable resistances - basically the gate voltage controls the resistance of the channel.
Vref (which in this case isn't exactly half of 9 volts, it uses a 10k/15k reference)
Yes that's OK, it should still work.