Multi-FX switching idea

[R.G.]

The CD4049 is supposed to be a level converter, so the single-ended transistor shouldn't be necessary.

Oh, yeah! That's right. Thanks - I'd forgotten that one.

Does anyone know if it is adequate with 8-bit resolution?

Well - let's see. Eight bits is 256 levels. If you approximate a sine wave to a maximum error of 1 in 256, that's 1/256 = 0.00390625, which looks like less than a 0.3% error at any point. I sincerely doubt it can be heard as as an LFO for a phaser. It would certainly not be a problem if the LFO was being low pass filtered by an RC, but that's not the case here. It's modulating the switches directly.

However, the human ear picks up repetitive noises very well. If the LFO has any sudden jumps at any point that recur, then the ear will pick that out as a repetitive funniness. This is what's called "zipper noise" in digital pots - the pots may be utterly silent, but changing the output level at a repetitive interval causes a perceived zippering. I honestly don't know whether that could even be picked up in a phaser.

I'm expecting that you'll tell us - yes?

The MXR envelop filter used switched component PWM for envelop sweep, but it was an analog PWM.

It may be that we would have to dither either the LFO output level or PWM timing to get rid of zippering. Or it may not be a problem at all, depending on the circuit.

[Transmogrifox]

Well, I'm sorry I've led you all astray    The CD4049 does not do level shifting in the way that I had indicated.

I should have looked at the datasheets before spouting about the CD4049:

The CD4049 is a level shifter in the opposite direction.  You can apply up to 30 Volts on the input and the output will not exceed Vdd.  The logic high input voltage is 7 Volts for a Vdd at 10 Volts.  The reason it worked for our senior design project from a 3V logic output is because the logic high input is 3V for Vdd=5V.  We were operating right on the ragged edge (very poor design in hindsight--but for getting the grade it only mattered that it worked).  Fortunately we were just driving a TTL circuit that illuminated a 7-segment LED display so we weren't operating at a high speed, nor was it a touchy application.

That said, you were right the first time, RG.  All of those components shown are necessary for a robust level shifting arrangement:
if one were to attempt to drive all of the CD4066 gates in parallel from the collector of the transistor, the sum of the input capacitance would filter the PWM unacceptably--thus the CD4049 as a buffer.