Tangerine Peeler: Correction and Question

[decc]

The correction: I'm hesitant to post this since no one else has mentioned it, but anyway in free electron's build report here he mentions the missing 4.7uF blocking cap. I found that I still couldn't get the darn thing to compress and after poking around I came to the conclusion that there is also a missing resistor between the blocking cap and the 1.5k resistor. On the original OS the volume pot acts as a reference to ground here but with it no longer part of this section of the circuit we need to add a 100k pull-down. Otherwise the reference is on the other side of the diode which somehow results in the envelope cap never charging. (At least that's the conclusion I came to after adding it fixed my problem.)

The question: I'm having a noise problem that I can't track down. Instead of the typical noisy quiet parts that would be expected with a compressor, I'm getting noisy loud parts. I can pluck a low E and hear hiss/static in the background which will fade as the compressor loosens its grip (meanwhile the level of the note stays constant.) With the release pot turned up it's even more obvious as the noise can outlast the note if you palm mute. As an experiment I removed Q2 and the un-compressed signal sounded clean. Is the JFET expected to be adding noise when it turns on?

[decc]

Replying to oneself is lame, but in the interest of anyone else that comes across this:

The 100k "release" resistor bleeds current off even during the initial attack, which limits the maximum voltage across the 4.7uF envelope cap and the gate of the JFET. If you replace the release resistor with a pot then this maximum level will vary according to the release setting. In my build a steady 1Vpp tone at the input with 100k release (so what should be a stock OS) results in about 750mV across the cap & JFET gate. If I turn the 500k pot all the way up this control voltage can get as high as 1.4V.

Now here's the problem: remember that bias pot that's such a pain to set? The correct setting, which keeps the JFET in the nice region acting like a voltage controlled resistor, is dependent on what voltage is to be expected at the gate. I was able to re-bias for long release settings but that threw things off for low release settings.

I tried a few arrangements of diodes trying to clip the control voltage but didn't stumble across anything that really worked well, and the particulars can vary with whatever JFETs you happen to have in the circuit anyway. So I guess what to take away from this is that the release pot mod does have a side effect (and that that bias pot is even more trouble than I had thought.)