Funny this should come up- I am currently venturing into a PWM phaser design myself!
The clock signal applied to the switching element is a pulse waveform whose duty cycle varies slowly from a high value to a low value and back again. Usually it won't go all the way from 0-100%, more like 10-90%. The frequency needs to be at least twice the highest audio frequency of interest, preferably much more. This might typically be 50kHz.
For my own experiments I started by building two 4-stage phase circuits that were identical except that one used JFETs, the other 4066 CMOS switches. I then drove both with the same 30kHz clock and audio signals, and examined the outputs to see which was better. (See below)
I found that the CMOS version suffered much less control voltage feedthrough, and also acheived more phase shift with the 10-90% PWM I had available (about 380 degrees with 4 stages). Changing the clock frequency didn't imporve the noise noticably. With this in mind, I'm going to stick with the 4066 as I develop the circuit.
One thing that is VERY important is to keep the PWM-generation circuit separate from any audio ICs, and use good PSU decoupling/regulation to keep the hash out of the audio circuit.
The next step for me is to design a low-cost PWM modulator.
FET circuit. Upper trace is the audio input, lower trace is the phase shifted output at the worst PWM setting.
CMOS circuit. Upper trace is the audio input, lower trace is the phase shifted output at the worst PWM setting.