I always look for the schematic diagrams that many manufacturers include in their datasheets. They usually show at least all of the important transistors that make up the gain stages and protection circuitry (biasing is represented as a current source for simplicity when drawing the schematics). This will tell you quite a bit about how the op amp will perform when put under certain "stressful" conditions, be it operating as a unity gain buffer or driving large currents. Some op amps are slightly overcompensated to ensure a good phase margin (one of the criterion for amplifier stability) as a UGB but this has an effect on the transient performance. More compensation means a slower transient response.
Doing a bit of research through a book like Baker's text on op amps at first may seem daunting, but there is a lot of more general information on different op amp topologies and their pros/cons. In his later books he delves into three stage op amps and crazy casocoding techniques that we don't really encounter with general purpose op amps (this is more for ultra low voltage CMOS design in sub micron processes
) but the basic information about general purpose two stage op amps is still there. He also delves into specifics when dealing with JFET and BJT based inputs (or entire amplifiers based on these devices if there is a performance benefit) as well as using PNP/P-Channel vs NPN/N-Channel based inputs (depends on if the common mode needs to extend to the positive rail or negative rail) or even amplifiers that use both P channel and N channel inputs in parallel. I have done the latter in a high speed op amp design and was really excited that I got near rail to rail performance when the amplifier was configured as a UGB, even on the bench!