Analysis Help, please? (EA Trem content)

[swinginguitar]

Was pondering the LFO section of the EA Tremolo - specifically wondering what the voltage swing of it is. Since the LFO modulates the gate voltage of a JFET, thus varying the resistance of it, my bet is it is a small voltage swing (possibly going negative?) in order to stay in the ohmic region of the JFET.

WHat would be your approach to analyze this?

As I haven't gotten into Spice yet, the only analysis tool I have at my disposal is Falstad's simulator. I built the circuit there and it shows that (depending on the depth pot), the modulation can swing a max of about -3v to +3v.

More to the point, I was pondering what would happen if I set up a PIC to generate the LFO that drives the gate of the JFET, and being that it would likely be 0v to +5v, would it need to be scaled and/or DC offset....

[PRR]

Simple oscillators swing rail-to-rail.

What version? If this: http://runoffgroove.com/eatremolo.html then "reail-to-rail" minus LED drop (and tiny transistor drop). Say 7V peak to peak.

The 0.47uFd blocks DC content.

The 120K 250K 68K reduces the swing. Full-up is about 5/7 of 7V or about 5V. Your PIC can swing it.

Why use 40,000 transistors when one will do the job?

[R.G.]

At least nonlinearity to nonlinearity, which is close  to the same thing for simple oscillators.

A real problem in the EA trem design - now that you mention DC offsets and scaling on LFOs  - is that it needs the big swing to swing negative on the gate to shut the JFET off a bit and get lower gain.

The EA as originally designed and in most of the clones has an N-channel JFET for the gain adjustment element. The source and gate are both pulled to ground in the absence of any LFO content, so the JFET sits pretty much full "on" as is. That's at the lowest rdson for the device. Swinging it positive doesn't do much toward lowering rdson any more. But the negative swings on the lfo do cause it to swing more negative than the source, and hence cause it to go higher resistance, causing the transistor's gain to go down. So about half the LFO waveform is kind of wasted in making a choppier sound, at least in sim.

I've often wondered at the EA trem sounding as good as it does.

One really interesting thing to do in the real world that I've done in some simulation is to tie the source of the JFET to a variable bias voltage to let you raise it a few volts. This also requires making the 20uF cap between the JFET drain and the transistor emitter be non-polar so it doesn't go leaky and spoil the fun. But doing this lets you offset the "zero" of the LFO waveform and get more of the JFET's rds swing inside the LFO swing. It makes it less choppy - as well as adjustable back to the original point if you make the bias voltage be a pot. The bias voltage on the source needs a cap at least 10x the 20uF cap, so call it 220uF at either 6.3 or 10V. This one can be polarized.

@Paul: why use 40,000 transistors when one will do?

As they said about Everest: because they're there. 

[Gurner]

If I'm reading the circuit correctly (& there's a good chance I'm not!), the Q2 LFO gate voltage will - depending on the position f the the depth pot - swing between 1V min & 5V max pk to pk centred around 0V (assuming a 7V pk to pk swing at Q3's collector)  ....which means for the positive half the LFO cycle swing, the Q2 fet source gate will be forward biased? (because Q2's source is tied to ground).

Personally, I'm with the 40,000 tranny crew...it allows you more variation/flexiblity wrt how you get to the top of everest

[Rob Strand]

>the Q2 fet source gate will be forward biased

When that occurs the voltage on the 0.47 cap will go more negative which then allows the gate voltage to swing more negative (and less positive with respect to ground).  I can't remember to what degree it happens in this circuit - and all my Pspice files as packed away.  It will also happen less when the depth is set low.  (Some RF oscillators use the forward Biased gate and coupling cap as a peak detector to regulate the swing to the JFET.)

Anyway, maybe someone can do the simulation ...

[R.G.]

It's called a DC restorer - or was back when it was being used a lot for TV/video signal work. Sometimes a DC clamp. The action is to 'clamp' the peak of the AC waveform that activates the diode to whatever DC voltage the diode's cathode (in this polarity) has. It works GREAT for waveforms where you can ignore the diode's offset voltage. Actually, this is the same action that causes DC blocking in tube circuits when the signal and bias let the signal drive the grid positive.

A DC clamp takes a variable time to react, depending on the resistances involved and what capacitances have to be charged. In this case, the capacitance to be charged is the one from the LFO to the JFET, and the equivalent Thevenin resistance of the resistors/depth pot between the LFO and the FET gate. And I suspect that  you're right, this is why the EA doesn't sound really choppy all the time. The clamping action of the JFET gate lets the operating point slide.

[swinginguitar]

What version? If this: http://runoffgroove.com/eatremolo.html then "reail-to-rail" minus LED drop (and tiny transistor drop). Say 7V peak to peak.

my builds most closely resemble the GGG version

Why use 40,000 transistors when one will do the job?

1) it's geeky cool
2) tap tempo
3) variable waveform

I've often wondered at the EA trem sounding as good as it does.

ditto....but it does!

Interseting thoughts, RG....so what your saying is by altering the bias voltage, you can drive the JFET "more negative" to get more use of the LFO waveform?

when i get time, i may plug in a PIC LFO as is just to see what happens and tweak from there.

[PRR]

> gate voltage to swing more negative...  I can't remember to what degree it happens in this circuit

Not a big bunch. Per R.G.'s "DC restorer/clamp" reference: this is a poor clamp because there is always at least 120K in series with the diode (Gate) and capacitor. Over-simplifying: charge through 120K, discharge through 250K+68K... only 3:1 difference. "Good" clamping is typically 10:1 or more.

me> 120K 250K 68K reduces the swing. Full-up is about 5/7 of 7V or about 5V. Your PIC can swing it.

Left un-said: the 120K drops the 7V to 5V. For 5V-only LFO you would omit (short) the 120K. However that "improves" the DC clamp action. Which just might not be an improvement.

You could move the 120K over to be in series with Gate. This has negligible effect negative-Gate, limits clamping/blocking on positive-Gate, staying closer to the honored original's actions while still working from 5V LFO.

While you can do a fair simulation of this, IMHO if you already have 40,000 transistors trained to wobble an LFO, a live-action breadboard may teach you more, faster, than any PC screen.

[swinginguitar]

While you can do a fair simulation of this, IMHO if you already have 40,000 transistors trained to wobble an LFO, a live-action breadboard may teach you more, faster, than any PC screen.

ROTFLOL!!!!!

I like the way you put things, Mr!

I will do just that in the next few weeks (given small kids, my circuit bending is limited to 10 minute bursts...hence the emphasis on the theoretical at this point)...

I'll write back what i find and perhaps get some more tweaking input from you guys

[swinginguitar]

Left un-said: the 120K drops the 7V to 5V. For 5V-only LFO you would omit (short) the 120K. However that "improves" the DC clamp action. Which just might not be an improvement.

without knowing the current, how did you calculate the voltage drop for 120k as 2v?

for 5v only, wouldn't you want to keep the 120k to keep the range under 5v?

[Gurner]

Left un-said: the 120K drops the 7V to 5V. For 5V-only LFO you would omit (short) the 120K. However that "improves" the DC clamp action. Which just might not be an improvement.

without knowing the current, how did you calculate the voltage drop for 120k as 2v?

If it's this circuit...

http://runoffgroove.com/eatremolo.html

You've got an (assumed) 7V peak to peak AC signal going into 120k 250k & 68K potential divider, therefore you do know the current (from I = V/R.....7/438k = 16uA (approx) which at a 7V AC signal makes for a  1.92V drop across the top 120k resistor (which takes it down to approx 5V peak to peak)

[swinginguitar]

...but where is that assumed 7v coming from? 9v less some amount of drop via the LED and the 10K? but again, we'd need to know the current drawn at that piont, right?

[Gurner]

...but where is that assumed 7v coming from? 9v less some amount of drop via the LED and the 10K? but again, we'd need to know the current drawn at that piont, right?

PRR indicated hits earlier in the thread....

What version? If this: http://runoffgroove.com/eatremolo.html then "reail-to-rail" minus LED drop (and tiny transistor drop). Say 7V peak to peak.

That's why I said "assumed 7V"

but again, we'd need to know the current drawn at that piont, right?

No, we only care about the current flowing through the potential divider I spoke of earlier ....so if it is 7V peak to peak signal swing at the top of the divider, then it becomes a simple ohms law calculation to work out the current through those three resistances (then another simple ohms law calculation to work out what the voltage swing is at each resistor junction)

[PRR]

> we'd need to know the current drawn at that piont, right?

Not really. The oscillator's load resistor is 10K. The divider is 120k+250k+68K= 438K, much-much greater than the 10K.

Stick a drinking straw in a river and suck. Yes there is current in the straw, but much-much less than the current in the river. Yes, the water level in the river drops while you suck, but very-very small drop.

So if we estimate about 7Vpp at the un-loaded oscillator, we may assume very nearly 7Vpp with the 438K loading. Perhaps 6.8V, and that's no big deal.

The FET gate current is much-much-MUCh less than any of the other currents. Like filling a hypodermic needle from the Nile. (At least this is true in the active region of the FET; as said this wacky circuit may sometimes drives the FET hard-ON which makes things kinda complicated.)

BTW, I didn't calculate the exact answwer for 120k 250k & 68K divider. I rounded to 120K 240K 60K, which is the same as 60K 60K 60K 60K 60K 60K 60K. The original took the MAX level between the 2nd and 3rd of 7 "60K"s, or at 5/7th of the seven "60K"s. Ah-Ha, 5/7 of 7V is 5V for all simple purposes. The calculator says 5.082V, but allowing for 438K loading on 10K oscillator says 4.9V.... bah, the max level to the gate is around 5V for all practical purposes. Remember the resistors may be 5% but the pot is likely 20% tolerance. Also the goal is to fling the FET gate and J201 cut-off can vary 0.3V to 1.5V. So there's no point in precise computations. That is, after all, WHY there is a knob. Partly for artistic effect, but also so you can find the sweet-spot despite great variation in part parameters.