Jack Orman:

In linear operation, a single cmos inverter operated in linear mode can only provide 30 to 40db of gain (31.6x to 100x). Max gain depends on the supply voltage being used.

The bandwidth also varies with V+. At 5v it is 710kHz., at 9v around 1.5MHz and at 15v it is about 2.5MHz.

Only unbuffered cmos should be used for linear operation. Th B-series buffered chips tend to be unstable when linear biased. The CD4049UBE is an example of an unbuffered inverter chip.

Current drain can be quite high for cmos operated linearly. Measure the current of your distortion when it is being driven hard to see how high it is going.

Add a resistor from the supply voltage to the V+ pin of the cmos chip. This will limit current to the cmos but also will reduce gain and bandwidth. Use 100 to 560 ohms. This is a subtle way to control tone & "feel".

The cmos input is very high impedance, but the output is high also. The stage after the cmos output should have a high input Z and low capacitance - minimum 1M, and preferably 10M! Unbuffered cmos outputs cannot drive a tone control stage properly. A capacitance load as low as 50pF will reduce the bandwidth of the cmos stage to 4kHz. Also, a low impedance load on the cmos output will drastically reduce gain. A 10k load can reduce the cmos gain to unity. It might be best to drive a jfet buffer at the end before a tone control or volume pot. (Bias the jfet buffer so that it can handle the large cmos signal without clipping.)


The open loop gain of an AE device is roughly ~30. While the input impedance of a CMOS inverter is huge, when you put the feedback resistor to bias it into linear operation, this resistor is "reflected" as a much lower resistor at the input of the inverter (this is called "Miller" effect - I think Randall Aiken has an explanation of this on his site).
If you use 31K as you used on the Insanity's 1st CMOS stage, this is reflected to the input as 31K/30 or ~1K. If you use the UB series, the open loop gain is much higher, at least 1000, so the 31K is reflected as ~31R or less. The input impedance of this stage will be 1K plus the 6.8K series resistor or 7.8K (or just 6.8K with the UB). With the 0.1u cap this gives a high pass at 200Hz (234Hz with the UB).
With Frank Clark's you have 250K (at maximum gain) that is reflected as 250R or less. There's no series resistor. 1M5//250 is ~250. With the 0.1u you get a corner freq of 6KHz... To be more accurate you need to consider the output impedace of the JFET stage (~4K) and this gives 374Hz. The lower the gain the higher this frequency will be (that's generally not desirable - you normally want the opposite to avoid IM with chords). The second stage does not have a series resistor also, so the corner freq will also be high because it is mainly dependant of the preceding c-mos inverter output impedance (which is low).

I think the design is prone to have bass loss, no blame on the c-mos chips. If you want to design for a good bass response, try the following:
1) When the inverter is capacitively coupled to the previous stage, use a big series input resistor;
2) When you up the input series resistor you need to up the feedback resistor or you'll have less gain;
3) When you direct couple inverters like you do on the insanity it's OK to have low series resistors or no series resistor at all;
4) Try the lower gain AE devices.