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DIY Stompboxes => Digital & DSP => Topic started by: Mikfish on July 08, 2024, 12:16:55 AM

Title: FV-1 Delay Memory Writing - Is it shifted?
Post by: Mikfish on July 08, 2024, 12:16:55 AM
Hey everyone,

I'm new here and this is my first post, please forgive me if I miss any of the rules about posting questions. I have a question about delay memory on the FV-1 pedal.

When an input signal is getting written to the delay memory on the FV-1, do the values in the delay memory get shifted as new values come in? Or do new values get written to the next spot in delay memory.

For example:
Time:    T0  T1  T2  T3    T4
Input: [0.2, 0.4, 0.5, 0.11, 0.6, ...]

Delay Memory
at:
T0: [0.0, 0.0, 0.0, 0.0, 0.0, ...]
T1: [0.2, 0.0, 0.0, 0.0, 0.0, ...]

Then is it...
Shifted?                          or  Not Shifted?
T2: [0.4, 0.2, 0.0, 0.0, 0.0, ...] or [0.2, 0.4, 0.0, 0.0, 0.0, ...]
T3: [0.5, 0.4, 0.2, 0.0, 0.0, ...] or [0.2, 0.4, 0.5, 0.0, 0.0, ...]

The reason why I'm wonder is because I'm trying to understand how input diffusion works from the "Effect Design" paper by Jon Dattorro.
When you have delay memory like this for example:
equ       in_diffusion     0.75      ;  k (coefficient)
mem     ap1_2              142       ; all pass delay memory size     

and then later you have...

rda       ap1_2# , -in_diffusion   ; read backwards from end of ap1_2 delay mem and multiply by negative k?
wrap    ap1_2 , in_diffusion       ; Write to delay mem, multiply by k, add to LR reg and then load ACC with result   

I'm kind of confused by what value is read in the delay mem above (is it the last value in delay mem because of #) and when we can start reading values from the delay memory after an input starts.   

Looking forward to hearing from anyone who might have some knowledge about this and learning from your expertise. I greatly appreciate it!

Thank you very much!
Mike



Title: Re: FV-1 Delay Memory Writing - Is it shifted?
Post by: Digital Larry on July 08, 2024, 08:27:33 AM
Quote from: Mikfish on July 08, 2024, 12:16:55 AMrda       ap1_2# , -in_diffusion   ; read backwards from end of ap1_2 delay mem and multiply by negative k?
wrap    ap1_2 , in_diffusion       ; Write to delay mem, multiply by k, add to LR reg and then load ACC with result   

rda       ap1_2#

This means to read from the memory location representing the end of the ap1_2 buffer.

wrap    ap1_2 , in_diffusion

This performs the all-pass calculation and writes the result to the beginning of the ap1_2 buffer.

As far as shifting input samples etc. goes that is all handled automatically in hardware.

DL
Title: Re: FV-1 Delay Memory Writing - Is it shifted?
Post by: Mikfish on July 08, 2024, 09:07:49 AM
That makes sense now. Thank you so much for answering that Digital Larry! I appreciate it!
Title: Re: FV-1 Delay Memory Writing - Is it shifted?
Post by: PRR on July 08, 2024, 10:06:19 PM
Welcome.

I do NOT know how FV1 works. But:

Shifting a 1000 slot array is 1000 operations. They can't be done in parallel unless you have 1000 slots of temporary storage. (i.e. a 2000 slot array)

"Shifting" by running a position counter 0-999 and back to zero is far cheaper. If you need the sample 345 samples away from 'now', simple math.
Title: Re: FV-1 Delay Memory Writing - Is it shifted?
Post by: ElectricDruid on July 09, 2024, 07:17:16 AM
Quote from: PRR on July 08, 2024, 10:06:19 PMI do NOT know how FV1 works. But:

Shifting a 1000 slot array is 1000 operations. They can't be done in parallel unless you have 1000 slots of temporary storage. (i.e. a 2000 slot array)

"Shifting" by running a position counter 0-999 and back to zero is far cheaper. If you need the sample 345 samples away from 'now', simple math.

It's kind-of amazing that analogue BBDs do actually do it the "shifting" way rather than the "moving pointer" way.
Title: Re: FV-1 Delay Memory Writing - Is it shifted?
Post by: potul on July 09, 2024, 12:30:58 PM
AFAIK, FV1 memory is not shifted, but the read/write pointers are moved automatically by the chip on each clock cycle. So it is transparent for the programmer.
Title: Re: FV-1 Delay Memory Writing - Is it shifted?
Post by: octfrank on July 10, 2024, 10:19:43 AM
In FV-1 there is a down counter that decrements once each sample period, this counter is added to the address in the instruction to generate the physical RAM address to read/write. This way all memory is "shifted" by 1 each sample period.
Title: Re: FV-1 Delay Memory Writing - Is it shifted?
Post by: Mikfish on July 11, 2024, 10:01:43 PM
Quote from: PRR on July 08, 2024, 10:06:19 PMWelcome.

I do NOT know how FV1 works. But:

Shifting a 1000 slot array is 1000 operations. They can't be done in parallel unless you have 1000 slots of temporary storage. (i.e. a 2000 slot array)

"Shifting" by running a position counter 0-999 and back to zero is far cheaper. If you need the sample 345 samples away from 'now', simple math.


Thank you for your help! I think I wasn't thinking about it correctly. It makes sense to me now though I think. I was trying to prove the concept of input diffusion to myself by making some smaller scale signals on paper and then running them through input diffusion which uses 4 different all pass filters with different delay memory sizes allocated to them.

I think now, it makes sense to me. If you're trying to diffuse the input, you're probably not trying to read from the middle of the delay memory array, but rather you'd want to read from the end of the delay array. So if you had a sample rate of 10kHz (just for example), and your delay memory = 100, then the first sample that came in would be in the last index of the delay memory 10 ms later right?