Hello guys, i'm trying to design a power filtering with a reverse polarity protection using a mosfet as the old and very good RG article.
(https://i.postimg.cc/zHyGjMDK/mosfet-schem.jpg) (https://postimg.cc/zHyGjMDK)
Mosfet:
https://www.infineon.com/dgdl/irfr9024npbf.pdf?fileId=5546d462533600a401535635f91d2132 (https://www.infineon.com/dgdl/irfr9024npbf.pdf?fileId=5546d462533600a401535635f91d2132)
For the test i make a veroboard and use a reverb circuit based on the btdr3h.
-Output power supply voltage: 9.42v.
-Voltage at V+ and VB+ with anything connected: 9.42V
-Voltage at V+ and VB+ with the circuit connected: 8.05v
1)Does anyone can explain me why the voltage down at 8.05v please?
2)Does this voltage down can affect the circuit operation?
3)Do you gus have a suggestion to not have this voltage loss?
Thank you so much.
Μπαλούμπα, nobody biases either p or n channel MosFet with its Gate to GND in case of he wish for low RD(on)..
Quote from: antonis on April 25, 2020, 02:50:17 PM
Μπαλούμπα, nobody biases either p or n channel MosFet with its Gate to GND in case of he wish for low RD(on)..
Bad english sorry, van you explain please?
Quote from: baloubass on April 25, 2020, 02:56:16 PM
Quote from: antonis on April 25, 2020, 02:50:17 PM
Μπαλούμπα, nobody biases either p or n channel MosFet with its Gate to GND in case of he wish for low RD(on)..
Bad english sorry, van you explain please?
Bad quote too.. :icon_wink:
Anyway, a p-channel MosFet needs a negative Gate-Source voltage bias to work in its "saturation" (no channel variable resistance) region..
In your schematic, the drain and source of the mosfet are reversed from what they should be.
Quote from: R.G. on April 25, 2020, 03:37:24 PM
In your schematic, the drain and source of the mosfet are reversed from what they should be.
Ok i have mirror it in fact?
[/quote]
Bad quote too.. :icon_wink:
Anyway, a p-channel MosFet needs a negative Gate-Source voltage bias to work in its "saturation" (no channel variable resistance) region..
[/quote]
😂😂 French T9 to write in english not help me.
What i have to do? Apply a voltage on the gate viaba resistor ?
Maybe, by declaring your nationality, some forum member could help you in written.. :icon_wink:
Quote from: antonis on April 25, 2020, 03:59:34 PM
Maybe, by declaring your nationality, some forum member could help you in written.. :icon_wink:
Done, and what i have to do, apply a voltage via a voltage divider
Do what R.G. noticed..
> the drain and source of the mosfet are reversed from what they should be.<
Drain should face R4 & Source face +9V..
Thank for the video.
Quote from: antonis on April 25, 2020, 04:43:29 PM
Do what R.G. noticed..
> the drain and source of the mosfet are reversed from what they should be.<
Drain should face R4 & Source face +9V..
Quote from: R.G. on April 25, 2020, 03:37:24 PM
In your schematic, the drain and source of the mosfet are reversed from what they should be.
Ok i will reverse the thing tomorrow. But i dont understand, because in all schematic i have seen, the +9v connect to the "D" and the circuit to the "S" pin according Drain(in), Source(out). i don't understand what i'm do wrong.
Your schematic has some flaws, like LED cathode pointing to +9V instead of GND, so plz verify first all "proper" polarities.. :icon_wink:
Quote from: antonis on April 26, 2020, 05:55:11 AM
Your schematic has some flaws, like LED cathode pointing to +9V instead of GND, so plz verify first all "proper" polarities.. :icon_wink:
Ok, i just write this schematic to make this post, for people see my global idea. I'm not take time etc... just for power section. So i don't think the reverse led on the schematic are the source of my problem. On the veroboard i just put the power section.
The reason I lost my voltage came from the RC filter I wanted to do. When i loaded the the voltage down at R4 in relation with the current.
Does anyone have a way to make a filter without loss voltage?
Thank R.G.
find the answer in an old post about balance between :
-RC filter voltage loss due to the current load.
-Desired frequency cut off.
-Space in the box.
See here (answer 19):https://www.diystompboxes.com/smfforum/index.php?topic=80063.0 (https://www.diystompboxes.com/smfforum/index.php?topic=80063.0)
Quote from: baloubass on April 25, 2020, 12:58:46 PM
-Voltage at V+ and VB+ with the circuit connected: 8.05v
Judging from your schematic, in case of voltage drop due to low-pass filter resistors, V+ & VB SHOULDN'T exhibit identical voltage drop..!!
(unless, of course, VB output provides zero current..)
Quote from: antonis on April 26, 2020, 10:13:42 AM
Quote from: baloubass on April 25, 2020, 12:58:46 PM
-Voltage at V+ and VB+ with the circuit connected: 8.05v
Judging from your schematic, in case of voltage drop due to low-pass filter resistors, V+ & VB SHOULDN'T exhibit identical voltage drop..!!
(unless, of course, VB output provides zero current..)
VB+ are connected only on the buffer section with just a 5088, the current are ridiculous.
V+ are connected with the other section contain the belton brick with lot of current.
I had checked with an overdrive circuit and the voltage loss something around 0.7v, less current than the belton.
I have swapped the "D", "S" connnection same thing with voltage down but lost the reverse polarity protection.
I reduce R4 24r to 4.7r and the voltage up around 9,35v or something like that.
I think i have to calculate a new RC filter around the 4.7r and play with the "uf value" to down the cutoff frequency, in relation with the space and capacitor size.
What cutoff frequency can be considered as good?
With 660uf and 4.7r = 51hz for the LC (R4+C1,C2).
33nf and 4.7r= around -35db at 20khz for the HC (R2+C3).
Does i need to reduce the LC filter or it's look good at this value? i have no reference to judge if it's a good value.
R2 + C3 is just another LOW pass filter is series with R4 + C1,C2..
(placing a second pole and, IMHO, loading enough preceding one..)
IMHO, again, R2 + C3 is useless, taking into account VB feeds a buffer with "ridiculus" current..
Without a complete circuit schematic, we can't tell for sure neither for HPF placement/configuration nor for its cut-off frequency..
P.S.
For current consuming circuits it should be a good idea to "split" positive supply rail (more than one V+) and place an individual LPF before each one...
(to keep low shunt cap value..)
Quote from: antonis on April 26, 2020, 12:20:06 PM
P.S.
For current consuming circuits it should be a good idea to "split" positive supply rail (more than one V+) and place an individual LPF before each one...
(to keep low shunt cap value..)
I don't understand this last suggestion.
Ok to form an high pass filter, i have to put R2 after C3.
I'm looking to create a filtering with the LC for the V+, and add a HC for the buffer section.
Maybe i have to make a LC and a HC with one V+ for the all of the circuit.
Quote from: baloubass on April 26, 2020, 12:41:13 PM
Ok to form an high pass filter, i have to put R2 after C3.
You're a bit confused about H/L pass filter items configuration.. :icon_wink:
(you may remove R2 wherever you wish but, as long as C3 remains a shunt cap you can't form a HPF..!!)
P.S.
High-pass filtering in power supply is a strictly forbidden action..!!
(I let you guess the reason for it..) :icon_wink:
hint: Power supply is (idealy) DC..
What is (or should be) DC frequency..??
Quote from: baloubass on April 26, 2020, 12:41:13 PM
Quote from: antonis on April 26, 2020, 12:20:06 PM
P.S.
For current consuming circuits it should be a good idea to "split" positive supply rail (more than one V+) and place an individual LPF before each one...
(to keep low shunt cap value..)
I don't understand this last suggestion.
It's just current sharing suggestion.. :icon_wink:
e.g. feeding 4 CE BJT amps of total current comsumption of 40 mA say, (each one of 10mA), result into a voltage drop of 1.88V across a 47R resistor (the series one of a LPF..)
By splitting the above configuration to 4 individual LPFs, you lower each circuit voltage drop to less than 500mV while keeping series resistor value the same..
By keeping resistor value the same, you also keep cap value the same - the last action is what actually counts, from space & money point of view.. :icon_wink:
Quote from: antonis on April 26, 2020, 12:56:38 PM
You're a bit confused about H/L pass filter items configuration.. :icon_wink:
(you may remove R2 wherever you wish but, as long as C3 remains a shunt cap you can't form a HPF..!!)
P.S.
High-pass filtering in power supply is a strictly forbidden action..!!
(I let you guess the reason for it..) :icon_wink:
hint: Power supply is (idealy) DC..
What is (or should be) DC frequency..??
Ok i understand to form a HPF i have to put the cap before the resistor and then the resistor go to ground not the cap.
And ok for the HPF in a dc power supply.
Does this schematic look good for you:
(https://i.postimg.cc/QVR97629/mosfet2.jpg) (https://postimg.cc/QVR97629)
Hmmm..
For across 4R7 resistor voltage drop, it should be OK..
(about 270mV taking into account 57mA V+ current draw - 9.42-8.05/24)
From LPF cut-off frequency point of view, 51 Hz are marginally OK..
If you're OK with -9db attenuation at 102Hz (-3db cut-off plus -6db for octave up) it's also OK with me..
(just take into account that 100Hz is the rectified mains supply in Europe..)
470μF for C1 & C2 should lower cut-off frequency to about 36Hz with no space/cost burden..
Quote from: antonis on April 26, 2020, 02:35:27 PM
Hmmm..
For across 4R7 resistor voltage drop, it should be OK..
(about 270mV taking into account 57mA V+ current draw - 9.42-8.05/24)
From LPF cut-off frequency point of view, 51 Hz are marginally OK..
If you're OK with -9db attenuation at 102Hz (-3db cut-off plus -6db for octave up) it's also OK with me..
(just take into account that 100Hz is the rectified mains supply in Europe..)
470μF for C1 & C2 should lower cut-off frequency to about 36Hz with no space/cost burden..
Ok thank you so much for your answer, you was really helpfull about the understanding what i do.
i think i will go with 470uf due to the space in the box. If i want a lower frequency cut-off increase the uF value but the space will be a problem, maybe with cms.
Hello, i have finalized the project and and now the pcb with for a 3pdt board with, mosfet polarity, dc filtering, centralized jack and dc connection fitted for 125b.
4x470uf and 4.7r for 18Hz Fc(2 on top and 2 on bottom).
Does it have difference between ENIG or standard finish? I've seen something about enig have a bad re-workability etc. For no smt board what's the avantage of enig finish?
(https://i.postimg.cc/bDyBFtq2/Capture-d-e-cran-2020-05-04-a-18-39-10.jpg) (https://postimg.cc/bDyBFtq2)
(https://i.postimg.cc/Yj1vxLhx/3pdt-mosfet-sch.jpg) (https://postimg.cc/Yj1vxLhx)
Continuing P.M. :icon_wink:
A project is a project, despite popularity interest..
Quote from: antonis on May 04, 2020, 01:25:06 PM
Continuing P.M. :icon_wink:
A project is a project, despite popularity interest..
I'm ok with you but i'm not looking for popularity etc.I don't know if poeple really read or find something with this kind of project. But you are right because, in the future if someone do a search about "polarity etc..." maybe it will be find an answer here, like me when i had make my search.
😉