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I have built the goosoniqueworx 7thheaven, which got me wondering about jfet biasing. All posts I read on here mention biasing via both Rdrain and Rsource. This works if you know Idss and Vgsoff, and are building your own schematic (which I plan to do after some more reading). However, effects like the 7thheaven typically only have a trimpot on the drain, not the source.

So, if I want more 'accuracy' than half of power supply (9v in my case), how do I compute this for a fixed Rsource? In this case the Fetzer valve calculations by rog do not really work.

On a related note: next project will be 'fetzing' one of the little supro schematics. I would think that Rsource is important in setting the gain characteristics, and that it is potentially better to only change the Rdrain compared to the original schematic. I am probably not completely right, but does that make some sense?

Thanks in advance, Hans

-Vgs & Source resistor set Drain current..
Drain trimpot sets Drain voltage..
You only need one trimpot for precise voltage setting..

>I would think that Rsource is important in setting the gain characteristics, and that it is potentially better to only change the Rdrain compared to the original schematic.<

Rsource is foremost important in setting Drain current..
Gain characteristics depend on particular configuration and may or may not involve Rsource..

Hey. I've been playing around with amp circuits in a box for a long time and realized that JFET is one trick pony. They create excellent and pleasant sound for medium to high gain, bearable sound for a clear channel, but they cannot simulate all the nuances. At the very least, we cannot simulate the value of the anode resistor of the lamp. In the future, I plan to revise my estimate of mosfet and op-amps in order to leave jfet in the past with all their disadvantages (need to tune each transistor, cold clean sound, little flexibility in circuit tuning).

Quote from: POTL on January 19, 2021, 03:29:44 PM
They create excellent and pleasant sound for medium to high gain,

Could you plz define the term "medium to high"..??

Hi Antonis,

Sorry if I wasn't exactly clear in my post. Offcourse only one trimpot (on drain) is necessary to get exactly half of supply voltage on the drain (9V with my 18V supply). However, I would like to set the voltage in the middle operating point (allowing equal voltage swing upward and downward). For as far as i know this *may* be similar to 9V in my case, but it may also be quite different depending on the characteristics of the jfet in question.

For example, my Q1 has the following characteristics:
Vgsoff 0,556V, Idss 0,110 mA (measured from drain to gnd), Rsource 820r, bypass cap 680nf
With these values an Rdrain of 62k gives me approximately 9V. However, does this also give me the middle operating point?

I would like to know since then I can play around with this operating point (for example, each consecutive jfet alternatingly just below and just above operating point).

@POTL: mosfets are high on my to-do list and I will try them out in upcoming projects. I have to say though, I like the emerald green distortion machine and the 7thheaven that i built so far. Do you recommend making the supro with mosfets?

Medium gain - vintage circuitry - Vox AC 30, Fender Tweed, Marshall Plexi (possibly JCM800). High - Mesa Rectifier, Soldano, Peavey, Orange (modern amps).

Quote from: hans h on January 19, 2021, 03:41:57 PM

@POTL: mosfets are high on my to-do list and I will try them out in upcoming projects. I have to say though, I like the emerald green distortion machine and the 7thheaven that i built so far. Do you recommend making the supro with mosfets?

I recommend trying initially, MOSfets have problems that I didn't like when I last worked with them (a few years ago, but then my knowledge was less), this is the noise of the transistor (it is stronger than any other kind of transistor or operational amplifiers), high frequency loss problem due to Miller capacitance. I can tell you for sure, avoid Zvex-style circuits, look at the AMZ Mosfet Booster circuits and use a stimulator to adapt it to the lamp frequencies, pay attention to the Catalinbread Rah circuit, at least you will get rid of the Miller capacitance problem compared to the Zvex circuits, but above the problem of transistor noise is worth working on, it is possible to use not standard 2n7000 / bs170, but for example LND150

Quote from: hans h on January 19, 2021, 03:41:57 PM
For example, my Q1 has the following characteristics:
Vgsoff 0,556V, Idss 0,110 mA (measured from drain to gnd), Rsource 820r, bypass cap 680nf
With these values an Rdrain of 62k gives me approximately 9V. However, does this also give me the middle operating point?

Now I'm confused a bit..
For 18V single supply, 9V is the midpoint quiescent voltage
I presume you are able to draw DC load line (V_DD on horizontal axis and V_DD/R_D on vertical axis) and AC load lines ( by replacing R_D with equivalent impedance) for various frequencies of interest..

Or did I miss your query..??

Any advice on the upper part of reply 4? (calculating Rdrain for a 'middle operating point' with a fixed Resource). Thanks in advance, Hans

Calculate I_D from:

(https://i.imgur.com/A3w2Coc.png)

Calculate Drain resistor from:

R_Drain = (V_DD/2) / I_D for a grounded Source CS amp..
e.g. for V_DD = 9V and I_D = 450μA, R_Drain = 10k

R_Drain = [V_DD - (V_DD + V_Source)/2]  / I_D for a CS amp with Source resistor..
(for Drain biased at (V_DD + V_Source)/2
e.g. for V_DD = 9V, I_D = 1mA and R_Source = 1k, R_D = 3k5

I cheat. I put it on the oscilloscope and dial in Rd, using 'known' Rs's from other peoples' work.  Trim Rd til it's doing what I want, then test by ear.  Easy but not everyone has a scope.   

Mainly this is because where something calls for a BS170, I may have a 2N7000 with slightly different characteristics.  Wanting to dig in to fully understand what's going on - that is a noble pursuit 8)

At the end of the day the specific JFET must come into play and you have to extract the JFET parameters out of the datasheet.

A simplistic approach is to use the table under green columns.    The results are all ratios and don't depend on the specific JFET.

You can start by nominating the |Vgs|/|VP| value, then look up the ratios in the table.

[See reply #16 for updated table]

The main observations are, in the middle range of |Vgs|/|VP| you can see that:

- RS/rds_on ratio only covers a small range, say 2 to 4.    The JFET parameter  rds_on is typically about 250 ohm and is quite a consistent parameter.    Switching JFET have low rds_on of say 50 ohms and a few JFETs like the J201 have higher rds_on.  rds_on is often not specified in the datasheet but it can be calculated from the formulas under the blue column.    The point is for a given JFET rds_on is fairly constant and the choice of |Vgs|/|VP| narrows the down choice of RS values to a small range.

The rest of the spreadsheet is just an example.  I've put the formulas in there for those who are keen to follow the numbered steps.

You can use the fetzer valve calculator,
http://runoffgroove.com/fetzervalve.html

However, keep in mind the fetzer valve use a fixed choice of |Vgs|/|VP.  Also they bias the drain voltage higher than 4.5V.

If you pick an OK RS then adjust RD to get the desired drain voltage you should be fine.

Is this for an "amplifier"? IMHO (I am aware of other opinions) an amplifier's plate/collector/drain resistor should be proportioned to the LOAD. Often 1/2 to 1/5th the load impedance. Then fiddle the cathode/source bias to set the plate/drain "correctly". Correct may be very low for maximum voltage gain or midway between Vs and Vdd for large signal performance.

I guess the confusion arises from me not knowing enough. I saw mentioned in many places that we can do better than biasing the drain simply at 9v. First it occurred to me that Rsource pulls the source up from 0V. But from your answer I gather that this is not the reason for deviating from 9V at the drain.

Looking at the load line, I can construct one. However, is there a formula for the 'characteristic curve' (intersection point characteristic curve and load line gives q point).

I guess I am just not sure how to start applying all this information to computing the 'best' Rdrain for a given rsource and given jfet with certain Idss and Vgsoff.

Thanks for bearing with me, Hans

QuoteI guess I am just not sure how to start applying all this information to computing the 'best' Rdrain for a given rsource and given jfet with certain Idss and Vgsoff.

If you nominate a VD, say 4.5V, you can calculate ID (see step 4c in spreadsheet).

From ID, and IDSS, you can get ID/IDSS.   Look up VGS/VP in the green part of the spreadsheet starting from ID/IDSS.  You can also calculate ID/IDSS from the "green" first formula; which is the same as what Antonis gave.

If you VGS/VP is at the extremes say greater than 0.8 and less than 0.2 you might need to reconsider your RD.

From the JFET's VP parameter and VGS/VP you can calculate VGS.

For this biasing scheme we know VGS = VS  which then lets you calculate RS from ID and VS;  from step (3) formula in the blue part.

Quote from: hans h on January 21, 2021, 02:17:21 AM
I guess the confusion arises from me not knowing enough.

As Paul said, you have to follow some rules of thumb.. :icon_wink:
e.g. for a CS amp, Drain resistor value should be 1/5 (or even lower) of what amp is supposed to drive (load - next stage impedance)
Then you have to calculate Drain current for midpoint bias..
(midpoint is considered 1/2 of V_DD + V_S..)
Drain current equals to Source current so you can choose Sourse resistor value for a desirable V_GS..
(in the mean of particular V_GS serves for particular Drain current..)

P.S.
Take a closer look to Rob's spreadsheet.. :icon_wink:
(it's a valuable provision..)

FYI, the spreadsheet has a bug.  |vgs/VP| should equal |VS/VP|.


(https://i.postimg.cc/d77s8FkF/JFET-Self-Bias-V11-2021-01-21.png) (https://postimg.cc/d77s8FkF)

Thanks all!

I started with the suggestion of Antonis.
ID = IDss(1-VGs/Vp)^2      Notes
      
Idss   0,11mA   0,2-1mA (datasheet, I measured at 9V)
VGs   0,106 V   Measurement Q1
VP   0,54 V?   Average value for J201's (diystompboxes thread)
VDD   19,85V   input voltage
Vsource   0,108V   
=> ID:      
0,071053361      
=> Rdrain:      
138,9237595   (k?)   62k in this slot gives me approx half voltage

It seems the jfet measures a bit low on Idss. I measured at 9V with only the multimeter (suggestion i found by someone).
VP is uncertain, some average value for J201's that I found on this site. All other measurements are with the
input voltage of ~19,85V.
I get the right order of estimate (139k compared to 62k in reality). What do  you think?

As a side note: from your comments I gather that if I cannot change Rsource, the best option is just to set Rdrain for half supply voltage. This is my only option for the 7thheaven, as only the Rdrain is a trimmer. However, this teaches me a lot for the next step that I would like to undertake: changing tube amp schems to fet stompboxes (starting with a simple supro). I am very grateful for all your comments.

I need some more time to reply to the other answers. Those will be next.

**added later**
Come to think of it, I probably should measure idss at the input voltage rather than 9v. If the relationship is linear, double Idss will give me half the Rdrain, which is approximately equal to the 62k I used

Quote from: hans h on January 21, 2021, 02:41:41 PM
It seems the jfet measures a bit low on Idss. I measured at 9V with only the multimeter (suggestion i found by someone).
VP is uncertain, some average value for J201's that I found on this site.

OK.. Some JFET parameters might exhibit uncertainty greater than that of Heisenberg principle.. :icon_wink:

A more realist way (among others..) is to take some measurements on particular items intended for particular build..
e.g.:
Connect Gate to Source (short respective pins) and apply an adjustable Drain-Source voltage (V_GS) starting from zero volts..
As the voltage increases, the Drain current will also increase up to a point and then stabize at a (almost) constant value..
The voltage at which the above occurs is the pinch-off voltage (V_P)..
For voltages at or above this, the Drain current is the saturation current (I_DSS)

(https://i.imgur.com/184v3we.jpg)

(both I_DSS & V_P can be measured by selecting DMM respective mod..)

Hi Antonis,

I do not have a continuously variable voltage source, but can take measurements at a few different voltages. Good plan to measure Vp device-specific as well. I'll try your method of measuring IDss as well, see if that provides a higher measurement (datasheet specifies 0.2 to 1mA).

Thanks, Hans

@GibsonGM: I do not have a scope. What I do have is somewhat similar: play guitar into looper => looper into pedal. Use a guitar cable with cap on hot side, ground to pedal enclosure. Then into amp => I can touch the circuit at various points to see how it sounds. I use that for debugging as well. That way I can also hear what each consecutive transistor is doing, but I need some more experience in the "tuning by ear" department.

Quote from: PRR on January 21, 2021, 01:02:12 AM
Is this for an "amplifier"? IMHO (I am aware of other opinions) an amplifier's plate/collector/drain resistor should be proportioned to the LOAD. Often 1/2 to 1/5th the load impedance. Then fiddle the cathode/source bias to set the plate/drain "correctly". Correct may be very low for maximum voltage gain or midway between Vs and Vdd for large signal performance.

I saw a similar answer of you in another thread, but do not know how to go about computing the load impedance.
This is for a stompbox based on a tube amplifier schematic. The 7htheaven is based on a bogner and after this I'd like to fiddle around with one of the small supro schematics. There will be some voltage gain, mainly to induce clipping in next stages. The whole impedance thing often has me puzzled. For example: input impedance of a stompbox depends on inp. impedance of the first transistor, AND on the value of resistor connected in series with input, AND on the value of resistor connected from input to ground (also anti-popping resisistor). Quite complex to me. Since I'm talking stompox, there is no speaker driving involved, just Q1 driving Q2 etc, and finally Q4/Q5 driving whatever comes next. So how to compute input impedance or load impedance of each stage?

Thanks in advance, Hans

Hi Hans,

Yes, using a debugging audio probe, you can listen to each stage as you go.  Looper would probably work just fine; I play a little as I go, just the guitar in since that is what I'll be using (old school).   I detach the coupling cap from anything following it and listen there; it may not matter whether the FET is loaded or not tho.  You'll find a range of reasonable sound on your trim pot that is quite narrow, in my experience.  You could start with a 10k or 20k pot (depending on your FET), tune until you get sound...measure the pot out of circuit, replace with a smaller pot and fixed resistance and use the smaller pot to 'tune it' if necessary.  Sometimes the 10k pot is enough.     I find that if you do it stage by stage with no pre- or post circuitry connected (so, one at a time as you build), if you shoot for 'clean and bright' tone, once they're all together they will clip nicely and not be buzzy or shrill.   Once several stages are together, it might be worth listening to them in sequence again to see what's going on.  Just how I do it (I'm sure many do this).  Interestingly I did find that 1/2 supply is almost never where you end up...I've also found when I do this 'manually', and THEN look on a scope, I've never ended up with a clean signal - what is musically pleasing is always a little offset (1kHz signal for scope work).     

It's very nice to know how FETs work and how to calculate impedances and so on - I do that for tube design.  Others have done enough design with FET boosts and preamps, I just copy what they've done, ha ha.  Then tailor them for different FETs I might have as I said above.   They were already paid to do all that hard work  :)

Sorry this was a double post. Removed it.

Quote from: hans h on January 22, 2021, 05:09:47 AM
The whole impedance thing often has me puzzled. For example: input impedance of a stompbox depends on inp. impedance of the first transistor, AND on the value of resistor connected in series with input, AND on the value of resistor connected from input to ground (also anti-popping resisistor). Quite complex to me.

Just apply Kirchoff's circuits laws (KCL & KVL) for each amplification (active) stage..
https://en.wikipedia.org/wiki/Kirchhoff%27s_circuit_laws (https://en.wikipedia.org/wiki/Kirchhoff%27s_circuit_laws)

Hint: Power supplies should be considered AC grounds and JFETs (devices) impedance infinite..

Could you plz post a particular circuit schematic..??

Hi Antonis,


(https://i.postimg.cc/kDBRtMsS/seventheavengworx.jpg) (https://postimg.cc/kDBRtMsS)

(https://i.postimg.cc/grQXy9tT/Supro1606.png) (https://postimg.cc/grQXy9tT)

After the information I got from all of you, this will be my approach:
1) 7thheaven: its already in the box so I can only fiddle with the trimmers and try different jfets. For this one I'll take the approach of GibsonGM: first bias to 9V. Next I use my "scope", trim each stage up or down and listen to the effect. My plan was to go down from 9V on the first stage, up from 9V on the second etc. This should in theory give me a bit more asymmetric clipping because the signal is inverted at each stage.

2) Supro 1606: I want to get this out on my breadboard. I'll start with two versions: version 1: use Rsource from the schematic, only change drain resistor (9V/ by ear) like on the 7thheaven. Version 2) compute Rsource AND Rdrain following the approach of Antonis/ Rob and afterwards the approach of Paul (for Paul's approach I'll probably come back for more advice). Goal of this all is to hopefully have a fun circuit and learn a lot about jfet biasing.

@ Rob: is it correct that I only see a png version of your spreadsheet?

@paul: I think something is off with my j201s. Using the stock Rsource (because it is already soldered on Vero), I have to use between 62 and 220(!) k Rdrain. This seems unreasonably high. Might this cause impedance mismatch between the stages? I feel that the tone is less clear (bit muffled) than it ought to be.

Quote@paul: I think something is off with my j201s. Using the stock Rsource (because it is already soldered on Vero), I have to use between 62 and 220(!) k Rdrain. This seems unreasonably high. Might this cause impedance mismatch between the stages? I feel that the tone is less clear (bit muffled) than it ought to be.

If you look at the table in Reply #16, which is roughly a J201,  you can see that as RS increases the required RD increases.
The table of RS and RD give you an overall view of how things are related.

Q2:  RS = 4.75k,  closest value in table RS = 4875,  requires RD = 44k
Q3:  RS = 10k,  closest value in table RS =10110, requires  RD = 78k

All high RD values.

The thing is JFET parameters vary from unit to unit.  To make things worse, some of the J201's you buy these days are not representative of the "real" J201's.   In this case the table doesn't  quite match your actual parts.

Q2: If you mess with R9 = 4.75k it could upset something since it works in conjunction with R10 and C4;  they would need to be tweaked.

Q3:  The lack of clarity would come about when R13 need to be set to a high resistance.   The cap C10 causes HF roll-off but the roll-off gets worse when R13 is set to a high value.    So perhaps set R13 to the mid position (50k) then adjust R14 to get the correct drain voltage.


You do get the loss of clarity issue with Q2 from R9 and C9 but you need more changes to fix it.

Thanks Rob, that is really helpful. One other thing I did not know is that the supply voltage changes the required Rdrain. I now went back to a 9v power supply which lowers the Rdrain quite a bit and therefore helps with the clarity issue quite a bit. The other thing I did was try every j201 in those two positions (q2 and q3). I selected the ones that gave me the lowest Rdrain.

Also tried 2n4548. This gave substantially lower Rdrain values but I lost the high gain, which is what I built this pedal for in the first place. For now i stay with the j201's and 9v power supply.

I'll play around with it a bit when the kids are not home to see how I like it. If it's not clear enough yet I'll also solder in a socket for r14.

Thanks a lot, Hans

Quote from: hans h on January 31, 2021, 02:00:03 PM
One other thing I did not know is that the supply voltage changes the required Rdrain.

It's just Ohms Law.. :icon_wink:

For a given Drain-Source current and also given Drain bias voltage (V_DD/2 say), Drain resistor value is directly proportional to power supply voltage..
e.g. for 1mA Drain current and +9V power supply, you need a 4k5 Drain resistor for Drain biasing at 4.5V (V_DD/2) where for 18V power supply you need 9k Drain resistor for Drain biasing at 9V (V_DD/2)..

CS amp gain is directly proportional to Drain resistor value(*) (either -g_mXR_Drain or R_Drain/R_Source) so for a given working current gain is directly propotional to power supply voltage.. :icon_wink:
(*) in parallel with any succeeding load..

QuoteAlso tried 2n4548. This gave substantially lower Rdrain values but I lost the high gain, which is what I built this pedal for in the first place. For now i stay with the j201's and 9v power supply.

2N5484's yes?

Anyway, most of the common JFETs will lose a bit of gain compared to the J201's when the source resistor is not bypassed.

You can increase the gain on stages where the source resistor is not bypassed using one of these methods,

(https://www.electronics-notes.com/images/transistor-common-emitter-amplifier-circuit-02.svg)

(https://i.stack.imgur.com/6whYJ.jpg)

However it can get a bit messy if there's already caps, like your Q1,  or caps + resistors, like your Q2.

You should be able to tweak the source resistor (and corresponding drain resistor) on the J201 to get a good result.

Thanks Rob,

Another helpful comment. I knew about bypassing using a cap but had not considered it. Not so practical for my current build, but really handy in tuning the supro 1606 schematic that I have in mind. Never noticed that the cap is sometimes in series with resistance and sometimes in parallel. What's the practical difference?

Quote from: hans h on February 07, 2021, 02:50:42 AM
Never noticed that the cap is sometimes in series with resistance and sometimes in parallel. What's the practical difference?

Practically none.. :icon_wink:

C3 in series with R5 bypass R4 where 68μF bypasss 820Ω while been in series with 180Ω..
(in the mean of, for DC purpose, R4 is considered Emitter resistor where 180Ω + 820Ω is also considered the same..)

For R4=1k, R5=180Ω and C3=68μF bias point and Gain/Frequency responce are the same for both configurations..