I have read that this circuit has a gate so that when your not playing you don't hear the sweep that's usually associated with analogue flangers.
Can someone show me where that is in the ada schematic please.
Here is the flintlock flanger schem
(https://i.postimg.cc/sv2L6cSR/Flintlock-Flanger-V1.jpg) (https://postimg.cc/sv2L6cSR)
Thanks
IC3.1 and 3.2 follow the amplitude of the input signal, and turn Q1 off when there is an input, and on when there isn't any.
Troubleshooting the PCB you had designed?
That's a peculiar design, isn't it? Can someone explain to me what that CD4007 is doing there? Seems like only a single PMOS is in use. Why not use a discreet device then? Is separate access to the body diode the issue? There must be discreet devices that have that and are smaller than a 4007, no? I am not clear on what the function is here. Is is just a switch between the R and R/C inputs of the 4047? If so, wouldn't and old JFET do?
Also, what's with the 4049? If maximum current is of the essence, why no parallelize three per channel and kick the redundant single inverters before the pairs? Outputs 10 and 11 of the 4047 are already buffered, are they not?
Most perplexing design choices these are...
Cheers and sorry for highjacking,
Andy
You may notice every circuit where they are substituting a 512 stage BBD with a 1024 stage one they use the 4049 buffer there to sharpen the clock's edges as they are being driven twice as fast. Perhaps it's not always necessary but ideal when you're driving a BBD above the datasheet's specs so it's not missing a beat.
I have to remind myself what the other chips are doing in that configurating. I had dug into that exact circuit on breadboard a while back to entertain ideas for using different BBDs. I'll let you know if I remember :icon_lol:
this bit:
(https://i.postimg.cc/fJcNZJzd/Flintlock-Flanger-V1.jpg) (https://postimg.cc/fJcNZJzd)
cheers, Iain
Quote from: Kevin Mitchell on February 03, 2021, 01:32:29 PM
Troubleshooting the PCB you had designed?
no my pcb works fine just curious about the gate functionality
Quote from: iainpunk on February 03, 2021, 05:10:46 PM
this bit:
(https://i.postimg.cc/fJcNZJzd/Flintlock-Flanger-V1.jpg) (https://postimg.cc/fJcNZJzd)
cheers, Iain
Cheers man
That's pretty clever, actually.
Quote from: Fancy Lime on February 03, 2021, 04:37:41 PM
That's a peculiar design, isn't it? Can someone explain to me what that CD4007 is doing there? Seems like only a single PMOS is in use. Why not use a discreet device then? Is separate access to the body diode the issue? There must be discreet devices that have that and are smaller than a 4007, no? I am not clear on what the function is here. Is is just a switch between the R and R/C inputs of the 4047? If so, wouldn't and old JFET do?
Also, what's with the 4049? If maximum current is of the essence, why no parallelize three per channel and kick the redundant single inverters before the pairs? Outputs 10 and 11 of the 4047 are already buffered, are they not?
Most perplexing design choices these are...
Cheers and sorry for highjacking,
Andy
About 4049, I suspect they want to keep phase using 2 stages of inverters in series 4007 is interesting too.
4007 is acting as a variable resistance to vary the frequency of the 4047 clock... This is how the clock frequency gets adjusted. Clever. A/DA used this on the Final Phase also.
4049 is acting as a buffer to keep the square wave clock pulse square so the BBD stays happy. I've used 4049U, 4049B and 4050B ICs here, it's not critical.
I do have a question about the FET used in the gate circuit... What is the ideal Vgs off voltage for this FET, does anyone know? I've tried FETs that were under a volt cutoff all the way to 3 volts cutoff and the "threshold" control doesn't seem to do much, in my experience. Maybe I don't know how to use it. Lol!
I didn't bother with the noise gate fet on my vero build.
Quote from: Kevin Mitchell on February 03, 2021, 04:49:53 PM
You may notice every circuit where they are substituting a 512 stage BBD with a 1024 stage one they use the 4049 buffer there to sharpen the clock's edges as they are being driven twice as fast. Perhaps it's not always necessary but ideal when you're driving a BBD above the datasheet's specs so it's not missing a beat.
I have to remind myself what the other chips are doing in that configurating. I had dug into that exact circuit on breadboard a while back to entertain ideas for using different BBDs. I'll let you know if I remember :icon_lol:
I understand what the 4049 is there for. What I don't understand is why it is not used more efficiently, which could be done with no extra parts or complexity.
Andy
Quote from: Fancy Lime on February 04, 2021, 05:38:05 AM
Quote from: Kevin Mitchell on February 03, 2021, 04:49:53 PM
You may notice every circuit where they are substituting a 512 stage BBD with a 1024 stage one they use the 4049 buffer there to sharpen the clock's edges as they are being driven twice as fast. Perhaps it's not always necessary but ideal when you're driving a BBD above the datasheet's specs so it's not missing a beat.
I have to remind myself what the other chips are doing in that configurating. I had dug into that exact circuit on breadboard a while back to entertain ideas for using different BBDs. I'll let you know if I remember :icon_lol:
I understand what the 4049 is there for. What I don't understand is why it is not used more efficiently, which could be done with no extra parts or complexity.
Andy
Do tell us more please!!
Quote from: StephenGiles on February 04, 2021, 07:30:35 AM
Quote from: Fancy Lime on February 04, 2021, 05:38:05 AM
Quote from: Kevin Mitchell on February 03, 2021, 04:49:53 PM
You may notice every circuit where they are substituting a 512 stage BBD with a 1024 stage one they use the 4049 buffer there to sharpen the clock's edges as they are being driven twice as fast. Perhaps it's not always necessary but ideal when you're driving a BBD above the datasheet's specs so it's not missing a beat.
I have to remind myself what the other chips are doing in that configurating. I had dug into that exact circuit on breadboard a while back to entertain ideas for using different BBDs. I'll let you know if I remember :icon_lol:
I understand what the 4049 is there for. What I don't understand is why it is not used more efficiently, which could be done with no extra parts or complexity.
Andy
Do tell us more please!!
Quote... If maximum current is of the essence, why not parallelize three per channel and kick the redundant single inverters before the pairs? Outputs 10 and 11 of the 4047 are already buffered, are they not?
I'm sure Mike Irwin who introduced the 4049 buffer to his SAD 1024 version of the ADA Flanger, would have configured the circuit in the most efficient way.