Not a stompbox by its own.. :icon_wink:
More like familiarization with, more or less, "complex" buffers and the way impedance is (or should be) dealt with..
(in respsect of T.D. Towers, Ray Marston, Douglas Shelf, to name a few collosal persons..)
All Zins are calculated and measured, athough they're much too optimistic (partially due to high gain devices and output light load) :icon_redface:
There will follow 3 Sheets, each one dealing with an impedance different "point of view" for better understanding and argument.. :icon_wink:
I'm pretty sure for draw/configuration/calculation flaws so plz feel free to point them out..
Also, any improvement concerning items/space save should be more than appreciated..
P.S.
I'm aware of much more simple circuits of equal or higher impedance but FETs suck (MosFets excluded) due to their lack of transconductance and op-amps bootstrapped bias resistors simply don't have fan.. :icon_lol:
Mainly bias configuration bootstrapping.. :icon_wink:
(https://i.imgur.com/nzF3NFJ.png)
edit: (40Ic x RE x RB) term comes for RB bootstrapped apparent value..
Which is calculated from 1/(1-A), where A stands for voltage gain [A = RE/(re + RE) and re = 0.025/Ic]
RE1 is placed there for a reasonable Q1 current (0.65/RE1), hence acceptable hFE1..
It could be connected directly to GND but it should load Q1 Emitter, where now is bootstrapped by Q2 B-E junction.. :icon_wink:
No Zin calculation formulas from here on 'cause they're getting too complicated hence practically useless..
Emitter resistor replaced with current source and push-pull configuration for better load current drive and linearity.. :icon_wink:
(https://i.imgur.com/Hqp2vRm.png)
:icon_eek: :icon_eek: :icon_eek:
Just realized that Sheet 3 is vanished..
Sorry guys, I'll have to recover it..
Only plan (A) has an input. On some, I can guess where to put an input, but some are ambiguous. (And you aren't trying to teach me.)
The inputs are on top, next to +9v.
> The inputs are on top
Thanks, I see that now.
(till Sheet 3 recovery..)
Instead of definitions via PMs, I presume it should be more informative to make a few interpretations here..
Input impedance can be segregated into 3 sectors, as far as impedance value concerns..
(actually, 2 sectors with 2nd one divided into 2 sub-sectors)
1st of them is bias configuration..
2nd is transistor input impedance..
(mainly concerning Emitter resistor in parallel with Load)
3rd is 2nd with Collector internal resistance (Early voltage divided by Collector quiescent current) taken into account..
Individual impedance raising steps should be implemented after critical thinking, in the way of apparent values comparison..
(it's useless to increase a 1M impedance when dominated by a 100k parallel one)
From incremental value point of view, firstly comes bias configuration, followed by Emitter resistor and finally comes Collector internal resistance, in a very brute approximation of 1/10..
(a 50k Thevenin equivalent bias configuration, a 5k Emitter resistor and 50k Collector internal resistor multiplied by a 100 hFE..)
Thank you very much for your work Antonis.
Are all the bias resistors scalable to deliver a 1M bootstrapped impedance or is there a limit to this?
Maybe you could also include the thd per buffer for given input signal.
Quote from: Max9999 on June 13, 2022, 03:37:42 PM
Are all the bias resistors scalable to deliver a 1M bootstrapped impedance or is there a limit to this?
I'm not sure I can get you..
Bias resistors values (actually their Thevenin equivalent) follow both 10 x R
TH < h
FE x R
E and R
TH > 10 x R
E rules of thumb..
The former for "stiff" bias configuration (practically independent from particular device current gain) and the later for insignificant Emitter loading (via bootstrap capacitor)..
Whatever bootstrapped impedance is exhibited for R
B comes from its actual (omhic) value multiplied by bootstrap factor..
(which factor can't be larger than 180 for a single BJT and 9V supply..) :icon_wink:
Quote from: Max9999 on June 13, 2022, 03:37:42 PM
Maybe you could also include the thd per buffer for given input signal.
It should be done, at a later time..
Almost all of them need optimization for linearity.. :icon_wink:
OK.. Sheet 3 is partially recovered.. :icon_wink:
(https://i.imgur.com/dD08Hbr.png)
I presume it should be kind of tribulation for those poor BJTs to keep going for impedances greater than 1G.. :icon_lol:
And a brief supplement.. :icon_wink:
Output impedance (max) & Voltage gain per configuration:
(A) = 27Ω / 0.99717
(B) = 27Ω / 0.99675
(C) = 17Ω / 0.99120
(D) = 18Ω / 0.99533
(Ε) = 18Ω / 1(*)
(F) / (G) / (H) / (I) = 5Ω / 1(*)
(J) = 0.99537 / 21Ω
(K) = 0.99262 / 19Ω
(L) = 0,99347 / 19Ω
(*) Unity means no 3rd digit measurable voltage difference between signal source and output..
(e.g. for a 1.414 Vrms)