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DIY Stompboxes => Building your own stompbox => Topic started by: stm on September 15, 2004, 06:24:51 PM

Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: stm on September 15, 2004, 06:24:51 PM
Hi all!

I settled to get 0.5 msec delay with the maximum possible bandwidth and using at most two quad opamps, intended for through-zero flanging without using a second BBD's and its associated frequency limitations, restricted dynamic range and noise problems. The circuit shown below is the result:

(http://tinypic.com/5777o)

The circuit is an analog time-continuous allpass network; it generates a 0.5 msec +/- 1% time delay from 0 to 6 kHz; frequencies above 6 kHz suffer no attenuation, however the delay falls down as frequency increases. With the values shown gain remains constant within +/- 0.2 dB from 0 to 20 kHz. The following curves illustrate this:

(http://tinypic.com/57783)

Component tolerance is critical , no only for the flat delay response, but to maintain the allpass or 0 dB attenuation characteristic across the audio band.  1% metalfilm resistors and 2 to 5% silvered mica capacitors must be used (hence the small capacitor values chosen).  Also, as a consequence of the op-amp saving topology used to implement the 2nd order all pass sections, every fourth stage in the circuit provides 26 dB of gain in order to maintain overall gain at 0 dB, so low noise opamps are recommended to avoid noise and hiss.

I think this circuit is "advanced" in terms of building complexity due to the large number of components and exact value dependence for proper operation. If there is enough interest, I would sell assembled and fully tested PCBs, so they can be used as building blocks and add-on boards for existing flanger designs. Just let me know.

I am posting this circuit for personal DIY use only. It is OK if you want to host it, as long as you credit me and retain all the copyright information.

As usual, I eagerly await the comments from our DIY community!  :D
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: Vsat on September 15, 2004, 08:12:45 PM
Wow.... very nice, stm!! Will you be building this soon?
Regards, Mike
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: stm on September 15, 2004, 09:01:01 PM
Mike,

My current priorities are:

1) 3-band universal tone stack (circuit already protoboarded & tested, just need to build it seriously, i.e. in a painted box with knobs and stompswitch!)

2) Dual MN3005 delay (status same as above)

3) MN3009 flanger/chorus/vibrato (haven't started with the prototyping yet).  Here I will try the analog delay line, perhaps with a SPDT switch to tuck it in the dry signal path!

If there is demand for kits on this I would consider devoting to the analog delay first.  For now I want to finish what I've started waayy looong agooo!  :roll:  :oops:  :cry:
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: Chico on September 15, 2004, 10:36:00 PM
STM

Very cool indeed.  In all honesty, it will take me a while to digest this circuit and all the other ideas that were discussed in the previous thread on this subject, but I am plowing through it.

I have just started a new flanger project myself and plan on testing out this concept in the near future.  My design is still very much a work in progress, so it may be a while, but I will let you know how it turns out.

Best regards and thanks for the build tips.

Tom
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: stm on September 15, 2004, 10:59:29 PM
Chico, good to see this stuff *could* be useful.

I've spent so many hours on this design, and really hope it is useful to somebody!

By the way, I found in digikey some 2% metallized poliester caps, which are cheaper and more compact than silvered mica.  In this case you can multiply by 10 the cap values (to use something more normal) and divide "frequency determining resistors" by 10.

Note that second order sections would require to change only the two upper resistors (105k and 309k), because the others on the + input just form a voltage divider and can be left as they are. Also, in the fourth opamp of each row, there is need just to scale the 215k resistor if the correspondig cap is changed.

Regards  :P
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: puretube on September 16, 2004, 02:21:47 AM
GREAT!

1 remark allowed: instead of buying expensive caps,
one could go out and buy a couple of handfulls of cheap ones
and measure them out: this can lead to <1% accuracy...

(look for capacity-meters/comparators elsewhere)
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: Mark Hammer on September 16, 2004, 09:58:32 AM
I salute your diligence and dedication, sir.

Mike/Vsat and I were discussing time-produced vs allpass produced "stagger" yesterday, and one of the things that occurred to me is that with time-produced stagger (i.e., the so-called "dry" signal is staggered/delayed by a small fixed amount so that the swept-delay signal has the opportunity to arrive at the mixing stage *before* the staggered signal once in a while), the amount of equivalent "phase delay" varies across the spectrum.

I'll try and express it more clearly.  If I delay the fixed signal by 1msec, the cancellation that results when it is combined with a swept signal does not occur instantaneously at all frequencies.  If I have a 10khz signal as part of the swept path, quite a few cycles of that signal will actually reach the mixer stage BEFORE the 1msec-delayed fixed signal gets there.  Naturally, the number of cycles that pass prior to any cancellation occurring (remember, it has to be the same waveform in anti-phase versions at the mixing junction for any cancellation to occur) will be fewer for lower frequencies, and more for higher frequencies.

In a sense, you not only have variation in the distribution of notches with flanging, but differential ONSET of cancellation because of the time differences.  Not having done the proper experiments, I obviously can not force the issue and say phase-delay will absolutely NOT yield the same sort of effect as true sample/time-based stagger, but the fact that musical effects are used with constantly varying, rather than steady state input signals means one has to set aside all those assumptions derived from textbooks and steady state signals, and consider real-world signals.

My gut sense is that true time-based stagger will produce cancellations in a different manner than phase-delay produced stagger, because of such differences in cancellation onset.  Again, that may just be a different feeling TZF and not necessarily a worse, better, or un-TZF-ey TZF.

A reasonable inference?  You tell me.
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: stm on September 16, 2004, 05:11:28 PM
Mark,

I'm pretty sure a time delay is a time delay independent of how you produced it.  In this respect, a signal through a BBD, or written in tape and read some time after, or an all-pass filter are equivalent, but IF and only IF the delay is the same across all the bandwidth of interest.

In this respect, BBD's and tape delays usually have LIMITED BANDWIDTH (above a certain point amplitude drops off), whereas an allpass filter has LIMITED DELAY from a certain frequency and above.

Having said that, the key for the different methods to be comparable is that they have similar or better bandwidths for flat amplitude and flat delay WITHIN THE AUDIO BAND OF INTEREST.

This poses the question of which is your audio band of interest.  In this respect, the circuit I proposed has flat delay up to 6 kHz, which I believe is reasonable for through zero flanging.  A typical flanger using BBD's may have frequency limitation around this point.  I agree tape flanging has better bandwidth, but also typical music has wider bandwidth than a guitar.

** I think the only way to tell is trying the actual thing **

By the way, the delay I propose can be reduced to 0.4 msec to increase flat delay bandwidth to 7.5 kHz if necessary.

Finally, regarding the fact that actual through zero flanging is not homogeneous in terms of which frequencies cancel first, I agree, since always one of the delayed signals has some slightly varying delay, that introduces slight pitch shifting.  This is independent of how you created the delay (IMO), and believe is integral part of the TZF effect.

Hope this makes sense.

Take care.
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: Vsat on September 16, 2004, 05:57:42 PM
stm,
Got the simulation running (finally... a resistor that had one end unconnected) and it works just as you say....NICE NICE NICE!
Regards, Mike
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: stm on September 16, 2004, 10:38:36 PM
Mike, good!

I still have one last card under my sleeve...

As I told you, each row of four opamps form one 4th order allpass + one 3rd order allpass with gain.  I can also use the very same topology (only with different component values) to obtain a single 7th order allpass stage.  The advantage is that the higher order would allow better bandwith (perhaps 8 kHz) at 0.5 msec.  The disadvantage is that component tolerance becomes more critical.

I have yet to cook the values for the 7th order to evaluate feasibility.  In other words, a working circuit in the simulator with perfect and stable values doesn't guarantee a real world working circuit.  So far I managed to obtain the poles of the transfer function. Converting them into the circuit is currently giving me a bad time, but I won't give up yet!

Regards,

STM
Title: Great work - valid point by puretube
Post by: MR COFFEE on September 17, 2004, 12:09:15 AM
Folks,
When we are trying to design LOW NOISE circuitry, the impedance needs to go down, or the the thermal noise of the resistors gets every bit as intense as BBD noise.

As puretube noted, we can forget BUYING 1-2% capacitors, if we simply SELECT our caps from a pool (pile) to get ones that match accurately. And even with different values involved, we can MEASURE our results (of an actually built unit) and tweak it into tolerance - a luxury unavailable on the production line, but quite available to the DIYer.

For all the op amps involved, may I be so bold as to suggest scaling values by at least 20 times downward to get the NOISE out  ...I really, really, REALLY have this thing about NOISE!!! ...UGHHHHH....
uh, sorry about that, folks. I must need to take my medication again... ;-)

BTW, many tweaked circuits for such purposes have an alignment proceedure and trimpots to compensate for overall device tolerances, i.e., adjust pot1 until phase delay at X hz. = 90 degrees, using a Lissajous (oh hell, I know that ain't spelled right) figure on a 'scope.

This is SUCH a cool thread. You folks are AWESOME..
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: stm on September 17, 2004, 12:17:08 AM
Well, as Duke Nukem used to say "Damn, I'm good"  8)

( :oops: sorry for that, just couldn't help it.)

I DID IT!

I really improved the above circuit just changing component values, so now it is implemented as two seventh order 0.05º linear phase allpass filters.  In plain english these means the following improvements to the above design:

1) I get 0.5 msec delay with over 8 kHz flat delay bandwidth

2) Using 1% resistors and 2% caps, a montecarlo analysis shows amplitude variation remains within +/- 1dB and delay stays within +/- 2%

3) I reduced capacitor value usage to just two different values (1nF and 10 nF) so getting 2% caps is easier

4) I reduced attenuation introduced by the second order stages from 52 dB (for the complete filter) to less than 12 dB, so there should be no noise problems now.

5) A single row (4 amps) can produce a respectable 0.4 msec delay with 5 kHz bandwidth, a great improvement over my very first delay circuit posted that achieved 200 usec with 5 kHz bandwidth and 4 opamps.

When I have time I will arrange the schematic and characteristic curves for posting.

Take care!
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: Mark Hammer on September 17, 2004, 09:58:05 AM
Damn, you ARE good!  (And is it me or do many schematics start to FEEL like side-scrolling games?  :)  )

As an aside, the benchmark through-zero sounds that many people are familiar with (and make them think "Geez, I wish I could do that") tend to be fairly broadband and cover a huge chunk of the audible spectrum.  No big surprise since tape-hub flanging was traditionally applied to multiple tracks during post-production (think "Axis, Bold as Love").  In discussion the other day, Mike/Vsat concurred that any attempts he's done at TZF (or just about any of his experiments in modulated comb filtering, whether mega-phasers or flangers) sound fantastic with white noise, pretty darn good with "music" (i.e., multiple sources mixed down to mono), and not that much more inspiring than regular stuff when applied to single instrument sources.  Of course, when you play a distorted power chord into an overdriven amp, the distortion introduced delivers up a lot of the bandwidth coverage needed to exploit these "electronic comb-overs", and you start to move into the zone of what will sound best with TZF.

There is a kind of balance between signal and device bandwidth to be considered for pleasing TZF.  I'm not going to speculate on what the required bandwidth is or will be, but a wide-bandwidth device fed a limited bandwidth (or rather narrow bandwidth) signal is unlikely to sound jawdropping.  Conversely, a full-spectrum coverage signal (let's go crazy and say white noise) fed into a limited bandwidth device will also make you go "That's nice, but less than I was expecting".  What one needs is a broad-spectrum signal fed to a wide bandwidth device.  Again, what that spectrum and bandwidth needs to be at a minimum is certainly outside the scope of my knowledge or experience.

Once again, I salute your dogged persistence in pursuing the ideal, and your skill in doing so.  Steve Giles, if he is reading this thread, is probably thinking "Yes, yes, dear the Andes are very nice.  Can we go home now?  I have some, er "stuff" that needs doing." :wink:
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: puretube on September 17, 2004, 10:19:57 AM
this co-incides with the "That Lady" phenomenon:
guitar thru "TZF" depends in its "felt intensity"
largely on the harmonic content at the input of the box.

No wonder most soundclips on the website of
"a currently marketed" TZ-flanger manufacturer
are using distorted guitar sounds...
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: Vsat on September 17, 2004, 10:51:04 AM
stm,
Attenuation  now only 12 dB! - that puts it way ahead of the previous design...great work.

Mark, puretube - other flangers/phasers have regen as an additional parameter for "strengthening" the sound. TZF doesn't have this, so has to rely on the quality of it's notches (and bandwidth). At least a couple of people have suggested to me that internal noise in a phaser/flanger may not be entirely bad.... it may even be essential in the case of tape flanging... it can help the ear to "delineate the moving comb" with otherwise spectrally-sparse input material.
Regards, Mike
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: Peter Snowberg on September 17, 2004, 11:17:37 AM
FANTASTIC work STM!!!! 8) 8) 8)

12dB.... Nice! :D
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: StephenGiles on September 17, 2004, 11:27:22 AM
Hi Folks - just arrived home in England after a 9 hour flight from Bonaire to Amsterdam, 1 hour to get through security!!! then straight on to our connecting flight back to London Heathrow, just 40 minutes. Despite a short 2 hour sleep after unpacking, all of which has absolutely nothing to do with thru zero flanging, I'm fighting to keep my eyes open so not really taking much of all this in yet, but fantastic work stm. Incidentally, I always hide a few important things when we go away for our annual holiday and having found my wallet, my LAN connector for my laptop and a few others, I just couldn't remember where I put my Stripboard ADA Flanger - bloody important -  a chap can't go on without that! I put it somewhere safe really to keep it out of the way of our cleaning lady in case she goes berserk with the vacuum cleaner!
Stephen
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: Ed Rembold on September 17, 2004, 12:14:18 PM
Very interesting thread!

STM,
I'd like to learn more about the filter topology you used,
Does it have a name?
or design program?

Thanks Ed R.
(Mike I. and Sean C.  nice to see you guys here-  been a long time)
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: Vsat on September 17, 2004, 12:44:13 PM
Hi Ed,
Nice to see your here!
Regards, Mike
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: StephenGiles on September 17, 2004, 03:57:35 PM
stm - any low noise FET opamp? Someone's bound to ask this - what would happen if the 10k resistances are modulated by a LFO?
Stephen
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: stm on September 17, 2004, 06:12:55 PM
"When you promise you are in debt" thay taught me when I was a kid.  So here I present my work. I will organize this post in three sections:

* The actual schematic and curves
* Building hints
* Answers to the questions that have arised in this thread so far

So here we go...

-------------------------------------
1) Actual Schematic and Curves
-------------------------------------

Here is the schematic:

(http://tinypic.com/5cqpg)

And here the performance curves as simulated with the nominal values indicated:

(http://tinypic.com/5cqqt)


-------------------
2) Building hints:
-------------------

Due to the great bandwidth increase with the new implementation, I finally settled for 0.6 msec and 7 kHz bandwidth.

Notice a slight difference between resistors R11 and R27.  This is for maximum amplitude flatness.  If you use them both equal to either value, you will have a 0.4 dB dip or notch (depending on which value you use) around 5 kHz.

The 20 nF capacitor should be made of two 10 nF in parallel, so you just need to buy two different values only (of course it was impossible to have this capacitor 10 nF due to the high Q of this particular stage which demanded a minimum value higher than 16.3 nF to be realizable, so I settled for the next higher convenient value.)

Each row has a 4.5 dB of gain at every fourth opamp, instead of 26 dB of my former design (so total gain of the two sections is around 9 dB -- the value of 12 dB I posted before was wrong, now it is even better!).  As such, I don't think low noise opamps are needed anymore. A TL074 or similar JFET opamp would do fine.


----------------------------
3) Answers to Questions
----------------------------

The topology I'm finally using is "7th order 0.05º equiripple phase allpass".  I haven't found information on the internet about this so far. I had to go to a 20 year-old book to find the location of the poles for this design, and from that, getting the w's and Q's and then start building the stages.  Finally, I used a symbolic math program (Maple) to develop the 2nd order section transfer function and solve it imposing the restrictions of simple capacitor values and minimum insertion loss.

The frequency determining components are the two upper resistors of each 2nd order stage, and the lower resistor of the first order+gain stage.  Scale them accordingly and you will move frequency and total delay.

The 10k resistors and its neighbours settle insertion loss AND overall gain flatness, so you can't move them or you will destroy the amplitude response!  Unfortunately, there is no easy way to use a photocell or other controlled resistor to tune the filter. I've thought of that so many times, but tight component tolerance preclude doing something like that with this circuit.  I've been thinking for along time about how you could build a BBD-less flanger!


Well, that's all for now folks!
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: puretube on September 17, 2004, 08:12:37 PM
a certain Hendrik Bode was a master of all-passing and ladder-filtering in the first quarter of the last century...
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: Vsat on September 17, 2004, 09:01:38 PM
stm,
Amazing!! Any chance of making a parts kit plus PCB available?
Regards, Mike
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: stm on September 17, 2004, 10:38:29 PM
Yes, I am thinking to develop a kit with PCB for this if there is more interest.  I think an assembled and tested PCB would be in order, specially considering the large component diversity and their particular tolerance characteristics, and the hassle of debugging a circuit like this in case some component is mounted in the wrong location.

Just wanna try it with an actual flanger to see if the through-zero effect really shows up, and then post some samples.  This may take at least a week, though, 'cause currently I've got no flanger to test it.

Also, a flanger based on an MN3007 will be at the limit, since it requires a 1 MHz clock to get near 0.5 msec delay.  John Hollis's Ultra Flanger is supposed to do this.

For my own design I plan to use a shorter BBD like the MN3009 which I happen to have.  This unit will allow to get as low as 0.15 msec or so, which would go great with the 0.6 msec analog delay.

In the mean time, let me know if there is more interest in this idea so I further develop it.
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: Ed Rembold on September 18, 2004, 06:53:55 AM
I'm gonna breaboard this thing and see how it works "in real life", and see just how "fussy" it is, with standard value parts. I'll scope it, and report back.
(thanks stm)

Ed R.
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: StephenGiles on September 18, 2004, 11:01:12 AM
Quote
Steve Giles, if he is reading this thread, is probably thinking "Yes, yes, dear the Andes are very nice. Can we go home now? I have some, er "stuff" that needs doing."


Hey Mark, I would gladly have stayed in the Carribean or back in Equador. It took 2 minutes driving out of the airport car park yesterday morning to experience the poor, very aggressive driving in the UK. England is a very shitty country now, and you really notice it after being away for a couple of weeks. Give me Equadorian/Peruvian Indian people anytime - lovely gentle friendly folks, unlike the yob classes in Engerland!
Stephen
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: stm on September 18, 2004, 12:01:03 PM
I've been tinkering around with the idea of using standard components, so I converted the 1% resistor values to 5% (E24 series) and tweaked them for best performance.  The following table summarizes the recommended values.

R1/R17 3.0k
R2/R18 56k
R3/R19 3.6k
R4/R20 22k
R5/R21 3.0k
R6/R22 7.5k
R7/R23 150k
R8/R24 100k
R9/R25 62k
R10/R26 20k/22k (different values on each row)
R11/R27 24k
R12/R28 13k/15k (different values on each row)
R13/R69 62k
R14,15,16,30,31,32 100k

Also, I did a Montecarlo analysis on resistor and capacitor tolerance to see what the curves would look like when you use real components.  The following table summarizes the error in the amplitude response:

1) Res 1% tol, Cap 2% tol: Amplitude +0.75 / -1 dB
2) Res 1% tol, Cap 5% tol: Amplitude +1.5 / -2 dB
3) Res 5% tol, Cap 5% tol: Amplitude +2.5 / -3 dB
4) Res 5% tol, Cap 10% tol: Amplitude +4 / -4 dB

According to the above, for my personal use I would try to stick to 1% resistors and 2% capacitors, however 1% resistors and 5% capacitors are still reasonable.

The following graph illustrates the curves for 1% resistors and 2% capacitors:

(http://tinypic.com/5n2vd)

And the following shows the curves for 5% resistors and 5% capacitors:

(http://tinypic.com/5n2w5)

By the way, for those who don't know, the montecarlo analysis runs many simulations changing the actual component values with a value with an error in correspondence to the tolerance specified. This simulates how would your circuit behave in case you pick real components from a box and install them without measuring or selecting them. The idea to run many many simulations is to see the family of curves that show where your actual circuit response will lie, which is useful to determine if there is chance that it may violate some design restriction or specification.

There are different ways of picking toleranced components in a montecarlo analysis, which are: gaussian or normal distribution, uniform distribution, and worst case distribution. I chose gaussian distribution for these simulations, which is the most benign of the three. For instance, worst case will look all the cases where the components had maximum tolerance deviation, which is very unlikely to happen.  Just wanted to clarify this because if you run your own simulation you will find different results according what you choose.

Kind regards,

STM
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: stm on September 18, 2004, 01:54:40 PM
For some strange reason I'm getting corruption on the four pictures in this page (they're hosted on tinypic.com), and sometimes they even appear in the wrong place.  Just in case, here are the actual links (sometimes it is necessary to press RELOAD if it doesn't show up properly the first time):

Here is the 0.6 msec schematic with 1% resistors:

http://tinypic.com/5cqpg

And here the corresponding performance curves:

http://tinypic.com/5cqqt

And here the montecarlo simulation with R=1% tol and C=2% tol:

http://tinypic.com/5n2vd

And here the montecarlo simulation with R=5% tol and C=5% tol:

http://tinypic.com/5n2w5

Regards,

STM
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: StephenGiles on September 18, 2004, 02:14:14 PM
Thanks a million stm, I'll go for the accurate values first. I don't have any 1% resistors to hand so for now I'll spend a couple of hours measuring 5% types to get as near accurate values as possible using 2 for each one. Knowing me, I'll mess about with modulation when I get some time. I wonder though just how usable TZF is in a live situation because surely your sound level will reduce drastically when the flanging hits the thru zero point. In a studio though, it is a different matter of course, and would be very flash to use in a guitar shop!
Stephen
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: Peter Snowberg on September 18, 2004, 02:31:07 PM
Awesome thread STM!!! 8)
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: stm on September 18, 2004, 03:07:04 PM
Thanks Peter, I've really enjoyed working on this!  Now's time to put it to the test...
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: Vsat on September 18, 2004, 06:30:31 PM
Steve,
Have your choice of  either summing or subtracting the fixed delay and variably-delayed signals. With summing, the two signals reinforce at the thru-zero point (and all  notches are gone).
Regards, Mike (busily soldering 1 percenters)
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: puretube on September 19, 2004, 03:44:23 AM
somebody mentioned "no feedbacking in a TZF" in this or the other thread

can`t remember whether it was on his site, in the H-C FX-forum, MusicToyz or here,
but Dave Fox mentioned s.th. about lots of experimenting and drawbacks
during R&D-ing his "Paradox" pedal, and how he was proud of having found a way, which signal to feedback where, to imply a "regen."-feature....

similar T-shirt here... :)
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: stm on September 19, 2004, 08:42:33 AM
Hi. Having analyzed the different topologies suitable for implementing Through Zero Flanging with a BBD + Analog Delay, I decided to post the possible schemes, since there is one option which is the most obvious but the least optimum. So here we go:

(http://tinypic.com/5pqis)

Regards,

STM
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: StephenGiles on September 19, 2004, 01:17:19 PM
Mike - I just got back from a play rehearsal for which my wife and I help out with some music. I used my stripboard ADA Flanger for the first time and I can safely say that it sounded great. I played an accoustic through a DI/Rat I made, plugged into a Behringer mixer. I connected the fx send to the ADA and the return into another channel of the mixer. It didn't like the low impedance output of the DI but behaved very well with the line level from the mixer. Hows the 1% resistors going? I can't face soldering anything yet, maybe in a couple of days when the jet lag has worn off!
Stephen
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: Vsat on September 19, 2004, 01:58:18 PM
Hi Steve (and list),
Good news...
Powered up stm's circuit last night (the 2nd latest version, since I had all the req'd values in 1% and 2% in the partsbox, built it on a PCB using a quick PCB layout, put a buffer stage at the network input). Tested it first with a sweep gen to make sure it was behaving properly. Then tried it with a flanger which gets down to 120 uS delay (network input connected to anti-aliasing filter output, network output connected to summing stage - the BBD does have a 12 KHz Butterworth which I didn't bypass). It does indeed give TZF sounds, somewhat different from my deltamod TZF unit, but still has the "kick" when you approach and go thru-zero. Tried both normal and inverse modes - have your choice of either cancellation (no signal) or reinforcement at the zero point. Works well with regen too - imparts a neat "hollowness" to the sound. Still preliminary.. took about 8 hours from start to first power-up yesterday.
Regards, Mike
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: stm on September 19, 2004, 06:27:49 PM
Some additional thoughts for getting a symmetrical TZF sound:

1) It is well known that for a "good" flanger sound a max to min delay ratio of 20 or better is required.

2) Also, it is believed that the clock frequency for the BBD should vary in proportion to the actual delay, meaning that the sweep remains more time at the low delay settings.

3) According to the above, one combination that would work is: fixed delay of 1 msec, min delay of 0.167 msec and max delay of 6 msec.  This has a max to min delay ratio of 36 times--quite good for flanging.  Also, the 1 msec fixed delay is at the geometric mean of the min and max delays, so if the sweep is done in this fashion the TZ effect will occur at the middle of the sweep and therefore will be symmetric.  The above could be achieved with a BBD like the SAD1024 and a suitable analog delay like the ones presented in this thread. However, the SAD1024 has two 512-stage delay lines, so in fact it can be used for both the fixed and variable delays!  I don't know why it hasn't been done before (or maybe I am not aware of this).

4) In order to get something usable for a MN3007 BBD, we will assume minimum delay achievable with this unit is 0.5 msec at 1 MHz clock.  So, lets design for 20 msec max delay, 0.5 msec min delay (40:1 ratio), and 3.16 msec fixed delay (the geometric mean).  In this case the fixed delay is too high for a reasonable implementation with an analog delay line.  A shorter BBD like the 256-stage MN3009 running at 40 kHz could do fine for this case.

5) I know the origin of this thread and the development of an all analog delay line was to avoid the usage of a second BBD unit.  I tend to be self critic, and even though I've worked a lot on the analog delay line, have to recognize that maybe it is still more convenient to use a second BBD for the task. To be honest, I'm not sure which is better, since both alternatives have their own costs, complexities and drawbacks.

Let me know what you think!  :wink:

STM
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: puretube on September 19, 2004, 06:43:00 PM
to be honest:
I admire your strive and labour - been thru similar experiments -
you got a great solution here!

For me: I`ll keep to the dual- (triple-/quad-) BBD solution
with proper layout and all precautions concerning
the known difficulties...

If there weren`t new reasonably priced BBDs on the market, I`d go Your way...

or: http://diystompboxes.com/sboxforum/viewtopic.php?t=25210
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: Vsat on September 19, 2004, 07:13:11 PM
Hey.... new ideas have to be tried!  Even if not always an optimal solution to the problem at hand, perhaps optimal for another use...

Currently I like the "karaoke" approach to TZF... easy to get very short delays...nice and quiet...
Regards, Mike
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: Ed Rembold on September 19, 2004, 07:57:00 PM
Mike,

When you say "karaoke" approach, do you mean, using a fixed digital delay for the "direct" signal?
Say it isn't so!

I very much like stm's original idea, I think it can be kicked up a notch (pun intended).

Ed R.
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: stm on September 19, 2004, 08:00:47 PM
Puretube:

Can you tell me which are those cheap IC's?

Mike:

Which is the karaoke approach? Is there an IC?

Regards,

STM
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: Vsat on September 19, 2004, 08:27:07 PM
Ed and stm,
The karaoke approach does indeed use the  Mitsubishi or Princeton echo chips.. one is a fixed delay, while the other delay is variable and voltage-controlled (analog clock, smooth operation.... no digital stepping). It is possible to make fixed or variable delays considerably shorter than the 100 mS minimum specified for these chips.
Regards, Mike
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: puretube on September 20, 2004, 02:06:02 AM
"karaoke approach", coz those chips
http://diystompboxes.com/sboxforum/viewtopic.php?t=25250
are mainly used in far east karaoke toys/amps for adding a little echo/verb.

I was referring to the stock BL3207/8 BBDs currently produced in China
-Smallbear got`em-
(as opposed to expensive scarce NOS/surplus chips)
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: stm on September 20, 2004, 09:53:06 AM
Puretube:

I feel you have some negative vibes about the NOS expensive and scarce BBD's.  Don't disregard that the MN3007 has over 80 dB of signal-to-noise ratio, as opposed to the 73 dB specified for the BL3207.  A chorus made with the latter surely needs some sort of noise reduction.

Regards,

STM
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: Mark Hammer on September 20, 2004, 10:15:30 AM
Quote from: stm
Don't disregard that the MN3007 has over 80 dB of signal-to-noise ratio, as opposed to the 73 dB specified for the BL3207.  A chorus made with the latter surely needs some sort of noise reduction.


Just for clarification, as the Matsushita line made the transition from earlier versions that used a higher supply voltage (MN30xx) to later ones that could work with much lower supply voltages (MN33xx), S/N ratios dropped.  I gather this had something to do with headroom available at the various supply voltages.  This should NOT be confused with any differences between the Matsushita and Beiling product lines.  It is entirely possible that Beiling's quality control is not the same as Matsushita's was for the same product; I honestly couldn't say but it still can't be dismissed outright as a possibility.  However it would be a mistake to immediately attribute S/N differences between the MN3007 (w/higher supply voltage rating) and the BL3207 to differences in product quality.

Bear in mind that S/N specs are derived from steady-state tones, not the highly varying music input signal such devices are going to process.  My sense is that if you broke down a typical music signal into those msec fragments where the input signal was at the max level that clean headroom permitted, and those fragments where it was far below that, the average S/N ratio of any BBD made by anyone is likely to be < 60db most of the time, in which case noise reduction of some form, whether brickwall lowpass filtering, companding or whatnot, will always be called for, whether one's layout is flawless of not.  

BBD's are like the Stephen Hawkings of the music processing world - they have much to contribute that is delightful and inspiring, but sonuvabitch they need a lot of technical support.
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: puretube on September 20, 2004, 10:40:19 AM
I just have mixed "availability-vibes" about the MN3007, which I`d otherwise prefer due to headroom&S/N.
If s.o. offered me 2000pcs for under 2K$, I might think things over...

For similar reasons I stick to 12AX7s in my tube-projects...


EDIT: just noticed Mark`s post (been distracted by a phonecall, right after starting this reply...), and totally agree with him!
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: stm on September 20, 2004, 11:15:16 AM
I never meant to imply that the BL units are lower quality than the MN (either made by Panasonic or Mitshubishi).  I am familiar with the specs variations regarding the different operating voltages.  In fact, the MN3207 has the very same 73 dB S/N ratio as the BL3207.

I'm pretty sure that the guys from BL didn't reinvent the wheel, and it is very likely they acquired the know-how and rights to produce mentioned IC's from Panasonic or Mitsubishi (or whoever owned them) after the product was discontinued.  As such, it is very likely to be a real close substitute.

I agree also with Mike's comment regarding the nature of music; it is very likely that you will ever take full advantage of the dynamic range of a device (and in consequence its S/N).  Anyway, specs are specs, and the lower the S/N the better.
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: puretube on September 20, 2004, 11:40:40 AM
OTOH, the S/N ratio is related to a nom. signal level which is about a quarter Volt, for less than 0.5% THD;
- well I don`t mind running a guitar signal of over half a Volt in there -
(I call it BBD-saturation),
as long as the bias is centered nicely, the "clipping" is tolerable, and the noise is a couple of dBs lower than this signal level...
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: StephenGiles on September 20, 2004, 02:02:28 PM
I put my English tongue in cheek and pontificate that the fuzz box brigade may not be over cautious about S/N ratio in such a flanger, and might "just" be happy to see the NE571 dealing with surplus noise! But that might up the parts count over the edge for some, unless perhaps the Bel Noise Reduction circuit is used which might make it worthwhile.

STM - surely if one half of SAD1024 has fixed delay, it will need a separate clock from the modulated clock used in the other half, and I'd wager $10 worth of pirate CDs from Quito that would introduce some fairly quaint noise to the equation.
Stephen
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: stm on September 20, 2004, 02:23:42 PM
Stephen:

I agree that if you build a dual-clock dual-BBD circuit on a protoboard, perfoard or single-sided PCB you will have all sorts of intermodulations, birdies and artifacts for sure.

On the other hand, if you use a double sided PCB, with one side devoted to the ground plane, keep separate analog and digital grounds just joined at a single point, use tantalum plus ceramic decoupling capacitors on the supply pins of each and every IC, filter independently both BBD's outputs, and do a careful signal layout (i.e. avoid running clocks near audio lines), my feeling is that IT SHOULD WORK PROPERLY.

I don't think its impossible. It's just harder to do (IMHO).

 :roll: Mmmhhh. this sounds like a challenge to me: "bust the don't use two unsynchronized BBD's myth"  :wink:

I have experience with high frequency digital and analog electronics, as well as microstrip and RF PCB design techniques. My former job was for a solid-state AM/MW transmitter manufacturing company, where I participated in the design of a 100 kW transmitter (currently on-air in Belo Horizonte, Brazil).

Regards,

STM
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: StephenGiles on September 20, 2004, 03:13:50 PM
STM
I see what you mean. PCBs of any sort are what other folks make to me so I wait patiently!!!!!!! Still now that you've mentioned it, I may well give it a try - on protoboard (is that breadboard?) at any rate. Too many things to do, not enough time! It's bad enough after 2 week's holiday getting used to routine household chores after being waited on in hotels.
Stephen
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: puretube on September 20, 2004, 03:18:02 PM
Quote
I don't think its impossible. It's just harder to do


absolutely correct!

(I`m quite sure you can do it.... :wink: )


Quote
Mmmhhh. this sounds like a challenge to me: "bust the don't use two unsynchronized BBD's myth"  


iirc, I posted a pic of my approach a few months ago...?...
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: stm on September 20, 2004, 03:57:26 PM
Puretube: thanks for the confidence vote!

Stephen: I call protoboard the white plastic board with many holes connected inside and stripes devoted for power supply. I tend to think of breadboarding as any means of building a circuit prototype.  That's the way I see those terms (english is not my native language).

Regarding the use of protoboard for the dual BBD task, I think you will be able to test your circuit and see how it sounds, however, you will have a bad time with the intermodulation, especially if you raise the regeneration level. I don't think it will be possible to eliminate those artifacts at this level.

After you have something you like, you may have to go for a well designed circuit and PCB as I described above.  It will be a bet or "leap of faith" to take that step, though.

Good luck!

P.D. I understand your housekeeping blues. Fortunately here in Chile it is still reasonably priced to hire someone to do the house cleaning, laundry and cooking.  When the person is sick or on vacation then my life as I know it collapses!  Just picture me trying to take a nap after a hard week at the office with my two daughters jumping on top of me.
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: StephenGiles on September 20, 2004, 04:34:42 PM
Ah - you live in Chile! You have probably read that we were in Equador from 2 - 12 September, a wonderful country. My wife, who is Anglo-Argentine, is planning our next holiday in 2005 to Argentina - can't wait. I don't think we will visit Chile this time, but we plan to return to Equador sometime in the future, and we may spend a few days in Chile at that time.
Stephen
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: stm on September 20, 2004, 04:40:58 PM
Stephen:

If you ever come to Chile just let me know so we can arrange a DIY meeting.  I'm pretty sure our wives will have plenty of things to talk about too.  :D

Regards,

Sebastian Tepper, aka STM
Title: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: puretube on September 20, 2004, 05:31:40 PM
Quote from: puretube


iirc, I posted a pic of my approach a few months ago...?...


before: (with "birdies")
(http://www.pure-tube-technology.de/xxx65)

after:
(http://www.puretube.de/xxx64.jpg)
Title: Re: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: StephenGiles on September 21, 2012, 01:50:55 PM
I discovered a link to this thread on which the last post was 8 years ago yesterday! Well worth another read through.
Title: Re: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: puretube on September 21, 2012, 05:27:46 PM
...dunno if it was mentioned in this TZF-thread or in another one,
but I still don`t like the total signal annihilation at the culminationpoint...
(that`s why the Flanger-Hoax got a switchable (frequency-dependant) "almost annihilation option")
[Mark: again not mentioned in the user`s manual...]

BTW.: "the market" just got a new TZ-flanger: The "Tunnelworm" by Mr. Black-pedalz...
http://www.mrblackpedals.com/products/tunnelworm
Title: Re: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: Mark Hammer on September 21, 2012, 06:31:10 PM
Again, most of the benchmark examples of TZF that we are all familiar with have usually been applied to a mix and seldom to a single instrument.

Maybe "almost annihilation" is what you want for a single instrument, and through zero is what you want for a synth or mix?
Title: Re: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: armdnrdy on September 21, 2012, 07:56:41 PM
I agree with "whole mix" and "annihilation" for a single instrument. If you've looked around Dave Foxes sight you would have found numerous mentions (almost to the point of arm twisting!) about putting a fuzz box or distortion before the Paradox. Dave even states that if you are the kind of guitarist that plays with a distorted amp and doesn't use distortion boxes, maybe this isn't the flanger for you!

I take this as sort of a disclaimer for the potential disappointed customer. If one plays through a through zero flanger without the fuzz/distortion in front, it is not near as impressive and "in your face" through zero flanging. (You have to listen for it or you'll miss it!)

I've been working on a variable gain, adjustable tone, fuzz/distortion section (glorified built in fuzz box) to incorporate into a through zero build that I completed. Along the lines of the Jet Phaser/Final phase idea but with a flanger.
Title: Re: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: StephenGiles on September 22, 2012, 09:49:49 AM
I agree with the you Ton, especially when the guitar is battling on stage with a bass player also trying to play lead and an over enthusiastic drummer! I think it is more of a recording tool than a stage tool as far as the TZF is concerned.
Title: Re: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: DiyFreaque on February 28, 2013, 09:45:19 PM
I'm with Ton - I like the Shanghai Bellings.  I used to look at the whole MN32XX family with a tad bit of disdain, but I've since discovered that they can do nice things for you if you're really nice to them.

I also think through zero can be really cool even on fairly sedate input signals.  The more harmonically rich the input, the more pronounced the effect, but even on "smooth" tones, the effect is far spacier to me than regular flanging.

These are Shanghai Belling BL3207s performing TZF on a fairly sedate (harmonically speaking) synthesizer piece.  It's positive TZF - I'm still trying to wrap my head around making that total drop in signal at negative through zero to do anything musical with it using a synth.  It's just the synth through the circuit to the recorder, no multi-tracking (or much musical talent, for that matter).

http://www.birthofasynth.com/sstites/HEADLine_10_TZF_1.mp3


Title: Re: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: stm on February 05, 2015, 08:22:55 PM
This is an old thread (10 years and a bit more), however I get asked from time to time about the schematics that have dissappeared because they were uploaded to a free image server.

I have improved the circuit a good deal in terms of noise performance, less variation with respect to parts tolerances, and using a single value of capacitors.  I'm ready to post the circuit and I tried to upload it to the Layouts Gallery (STM Guitar FX) so it will survive longer than in a free image hosting site, however during the past two days I am getting an error message #7 (whatever that is) when trying to upload the file.  The file is around 35 kbytes in PNG format, so it is not a matter of size :icon_eek:

Have anybody have experienced a similar issue or have a clue as to what could be causing this?
Title: Re: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: Tony Forestiere on February 05, 2015, 08:31:24 PM
Have find another hosting company or do something with the gallery. Out of space.
Title: Re: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: snap on February 06, 2015, 01:59:43 AM
http://www.diystompboxes.com/smfforum/index.php?topic=109958.0
Title: Re: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: stm on February 06, 2015, 07:27:54 AM
This is a revised version of the analog delay circuit.

You can cascade four identical circuits (for a total of 8 opamps) to obtain a fixed 0.5 msec delay up to 6 or 7 kHz.

This revision has several improvements over the previous circuits, including:

- The basic building block ia a 4th order section instead of a 7th order section, so the resulting response is less affected by component tolerances
- The building block topology has unity gain and does not need a gain recovery stage at the end, therefore being less noisy
- The capacitors are all of the same value, and less different resistor values are needed, therefore making the build easier and less prone to error

In any case this circuit requires precision components, 1% metalfilm resistors and 5% or better capacitors.  Failing to do so will result in dips/peaks in the amplitude response which will accumulate if several cascaded stages are used.

(http://i62.tinypic.com/2prdwjl.png)
Title: Re: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: ~arph on February 06, 2015, 11:17:54 AM
Nice!

(so for 500ms I would just use 8000 opamps  8)
Title: Re: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: stm on February 06, 2015, 11:45:56 AM
Nice!

(so for 500ms I would just use 8000 opamps  8)

Yes, or a 170 meter (560 feet) pipe with a speaker in one end and a mic at the other  :P
Title: Re: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: rx5 on September 18, 2021, 11:38:35 AM
This is a revised version of the analog delay circuit.

You can cascade four identical circuits (for a total of 8 opamps) to obtain a fixed 0.5 msec delay up to 6 or 7 kHz.

This revision has several improvements over the previous circuits, including:

- The basic building block ia a 4th order section instead of a 7th order section, so the resulting response is less affected by component tolerances
- The building block topology has unity gain and does not need a gain recovery stage at the end, therefore being less noisy
- The capacitors are all of the same value, and less different resistor values are needed, therefore making the build easier and less prone to error

In any case this circuit requires precision components, 1% metalfilm resistors and 5% or better capacitors.  Failing to do so will result in dips/peaks in the amplitude response which will accumulate if several cascaded stages are used.

(http://i62.tinypic.com/2prdwjl.png)

hi STM

could you please re-upload this?

going the op-amp route would be much practical than going with the now NOS 3101/3007. would like to try this out on my buffered mistress.  :icon_mrgreen:

cheers
Title: Re: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
Post by: rx5 on September 19, 2021, 11:38:34 AM

 ok nvm.. found *more*stuffs on the net.. and sim' d it on Ltspice. yep flat response and unity gain at the inverted output. this was with TL082 and resulted in 100uS phase delay per op-amp. total of 400uS per quad chip. add another dual for the signal inversion & strong midpoint voltage.

now I can still remember the older 741 and 324.. how where they being clunky devices? slow?? would it add up the phase delay?  :icon_mrgreen:

hmmmmmmm