Hoping someone can point me in the right direction here....
I've looked all through this datasheet but I didn't really know what to look for.
http://focus.ti.com/lit/ds/symlink/cd4069ub.pdf (http://focus.ti.com/lit/ds/symlink/cd4069ub.pdf)
How do I determine how many gate-inputs can be driven by another gate's outputs before needing a buffer?
There are several tables and charts with current values but I'm not sure which ones apply.
The problem is, the number is variable, not like the old TTL fan in and fan out specs.
A CMOS input is a capacitor. The outputs are current limited. How many capacitors can you drive with 1.3728ma of drive current?
Somewhere between 0 and infinity, depending on how long you can afford to wait.
The fan out is frequency dependent. You have to guarantee that all the input capacitors - and other junk if you put things other than CMOS inputs on the net - will charge to above/below the input thresholds by the time the next clock pulse comes along.
So the answer can be computed by knowing that I = C dv/dt. We know I from the current graphs which list it as a variable depending on the power supply voltage. We know dv, the difference between the long-term resting voltage of the output and the furthest threshold voltage, and we know dt as the time between clock pulses. We can compute the C that is the max capacitance that can be driven in that amount of time. We subtract the wire capacitance from that, divide by the input capacitance of a gate, and that's the number of gates we can drive without a buffer.
Sorry - it's not easy.