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Since some time the use of a source trimmer instead of a drain trimmer to bias JFET class-A amplifiers has been gaining adepts.  I would like to ask the promoters of this technique what are the actual facts that support SOURCE over DRAIN bias adjust.

So far the arguments I've seen are oriented to demean those using drain trimmers with arrogant statements like comparing drain biasing to a "parlor trick" or referring to source biasing as "what the skilled technician would do".  Of course none of us want to do a "parlor trick" in a guitar pedal intended for our personal use, and we all want to be compared to a "skilled technician", so +1 to the marketing dept.  This campaign has been quite effective, as the other day a "DIY veteran" referred apologetically to his use of drain trimmers as they still did the job.  And heck they do the job!

Perhaps the drain trimmer got a bad reputation since some DIY circuits have poorly chosen drain trimpots which either make the adjustment too difficult (if the trimpot is too large), or impossible (if the trimpot is too small).  This reasoning does not favor the use of a source trimmer, as a poor choice of the source trimmer and/or fixed drain resistor can produce equally ill results.

What next? Something evident is that as a drain trimpot is adjusted, the output impedance of the JFET stage varies accordingly, and so changes the frequency response due to the loading effect of following capacitors, to say the least.  OK, this seems like a good argument.  But the valve circuits that usually inspire JFET circuits all have large output impedances, in the range of 30k to 200k (by the way, the actual output impedance of a triode stage is a value SMALLER than the plate resistor, something typically between 1/3 and 2/3 the plate resistor, depending on the operating point).  So, having some output resistance is not bad after all, in fact you actually NEED IT so those tone control capacitors tied directly to the drain (or plate) behave as expected.  Ergo, what we would like is to have a fixed output resistance when a drain trimmer is used so as to have a repeatable and well-defined behavior...

...And it can be done. Rearranging a couple of wires around the trimpot you can have CONSTANT output impedance equal to the total trimpot value regardless of the trimpot's rotation.  The change is pretty obvious, yet I have never seen it used or mentioned before, so I decided to call it "stupidly wonderful drain biasing" or SWDB, following Mark Hammer's philosophy when naming his "stupidly wonderful tone control" or SWTC.

So, this is my newest "parlor trick": http://www.aronnelson.com/gallery/main.php/v/STMs-Circuit-Ideas/SWDB.png.html (http://www.aronnelson.com/gallery/main.php/v/STMs-Circuit-Ideas/SWDB.png.html)

After these arguments I see both biasing methods are tied, unless there is something else I am missing.

i just hate when someone comes up with this kind of ridicously simple solutions..makes me feel dumb!!!!

sebastian...la cagai pa seco!!! maestro!!!  ;D

  That looks like an elegant approach.
  Depends on the JFet, and what kind of gain structure you want, if the source resistor stays the same and the drain resistor gets huge to bring bias into focus...the gain of course will have been altered.
  ...A small handful of your favorite Jfets...a drain trimpot.
  A trick I liked...start with larg-ish source R, make long-leg version above board, then tack on a pot or a larger resistor on it [parallel reduces the R]...then get it biased and be able to better control the gain structure.
  Some schematics I believe actually press the Jfet into a 'corner' [for the effect that has] and some Jfets refuse to bias like that, numerous Jfets may not bias there...
  You can get your last Jfet to bias, one way or another...
  But I just pulled 3 transistors with 3 trimpots from an amp thing I built and tweeked and cajoled into working different ways this year [plenty of bias diddling, and put them in Mu amps...the rest of that amp-thing build had it's wires clipped so the board would come right out. This has happened numerous times.
 The Mu Amps biased right up, N/P 

Changing the drain resistor changes the DC bias point and gain.
Changing the source resistor changes the DC bias point and gain.
Changing the gate voltage changes the DC bias point. You can't change the gate current except by sacrificing all gain on positive swings.

The impedance of the drain is somewhat immaterial - just ensure that what follows it is greater than 10x the drain impedance worst case. If you can't do that, use a buffer.

The real story is that JFETs vary. Learn the variations for the parts you use, and design to make the variations not matter, or tune per device. It makes no sense to say that tweaking source, drain or gate is better than the rest UNLESS YOU CAN ARTICULATE WHAT EFFECT THE CHANGE HAS ON THE REST OF THE CIRCUIT CONNECTED TO THE JFET.

Let me get this out of the way first- Re. people being "demeaned" for using a drain trimmer instead of a source trimmer- I haven't seen it. I mentioned the source trimmer a couple times as a "possibly better hack" for reasons that will follow. I referred to the drain trim as a parlor trick one time, but that had less to do with the particular technique and more to do with a general attitude I perceived at that time. I don't really care what techniques people use as long as they are happy with their results. This is not a manufacturing forum but a hobby forum so although consistency is a great design goal, it's not absolutely necessary. We already pre-select bjts and etc for other circuits that do not account for device variations in their design. But it does bother me when I see people being encouraged to settle for the status quo and not think outside the box because it's "too hard". It also bothers me to see someone go to the trouble to answer a question in detail, only to have it ignored or fluffed off. With enough of that, people will quit answering questions. Without people answering questions you have no forum.

Now back to the real subject - Changing the resistance of the drain circuit changes the gain, which is IMO more of a problem than output impedance changes (which can still be a problem too). Gainwise- changes in the source resistance due to using a source trimmer can be "masked" somewhat by using a) large bypass caps on the source that go to ground, or b) large bypass caps that go to an RC combination that goes to ground. The RC combination can be used to tune a HPF freq shelf, much like in a cathode circuit of a tube circuit. This works within limits- only if the source biasing trim is set high enough to have a negligible effect on the "R" in the RC circuit. If you use large drain resistors (100k for example), this helps keep the necessary source resistance high enough to reduce the effect it might have on any RC tuning.  If you just try plugging & playing tube amp topologies into it you will find other limitations with it as well. It's just a hack, but it worked well for some J201's I tried it with. I have not tested it across a large number of J201's or other JFET types.

There is no free lunch with any of these techniques. In the end, if you are building a one-off and you are happy with how it sounds using drain trimmers or whatever- none of this matters. The issue comes up where you want to design things that are repeatable and sound consistent. We've gotten to the point with bjt's and op amps that we can design stuff that sounds fairly consistent from one build to the next. It would be nice to find a way to do that with JFETs too.

IMO, the best way to mimic the sound of a particular amp is to do some analysis of the amp in question with a scope and spectrum analyzer. Then pick your building block of choice and start from scratch, much like LXH2 with the marshall/fender sim, or the German gentleman (can't remember his name) did with the AC30. Note they both used op amps as their building blocks because they are consistent and results are repeatable. I suppose you could follow a similar procedure with JFETs but you would need to use biasing techniques that take the JFET variations into account if you wanted repeatable successful results. Then again, IME it's just a heck of a lot easier to build a tube amp... :icon_wink: :icon_wink:

I seem to keep coming back to constant current bias.  As long as you keep I_D lower than I_DSS, then I_D becomes independent of the JFET.  In practice it's really not hard to do.  The only reason not to is the extra transistor required, but that's still cheaper than a trimpot.

Yes, we discussed that in another thread Alex. :icon_wink:

It's next on my list when I get back to the breadboard. I'm looking forward to trying the ideas you and others have tried from AN102! :icon_wink:

IMHO, one thing i like about fets is the fact that they vary..IME, for fet versions of tube amps, the variations are small (i allways end up setting the trimpots at the same position for all fets, by ear) so i don´t think variations in fets are too significative..

i´ve built about 6 or 7 jfet preamps (dual rectal) and i´ve founmd that far more important is the choice of filtering values that fet biasing,. Although all preamps i made sound a little different, i found that they are as consistent as any tube amp..IMO Tubes are far less consistent than jfets , it depends on the brand, the hours used, how old they are, the outlet voltage, even two identical tubes may not sound the same.

So i like that "unpredictability" about jfets. The results are always good, but from time to time you get a fantastic device, just like with tubes, and even guitars!!..

As dougH said, if we want consistency, we should go with opamps, but there is something about fet´s tone that just doesn´t let me go back to opamps..for me, jfets are the ultimate tube equivalent, not because how they sound, is because what they MEAN..

Quote from: dschwartz on August 13, 2008, 11:20:21 PM
i just hate when someone comes up with this kind of ridicously simple solutions..makes me feel dumb!!!!

sebastian...la cagai pa seco!!! maestro!!!  ;D

Hola Daniel.
Don't worry, when Mark Hammer came up with the SWTC I felt dumb too :icon_redface:
You are "seco" too. You've done a terrific job with those hot rod dual rectos and valve amps!  :icon_cool:

Quote from: stm on August 14, 2008, 09:56:51 AM

Quote from: dschwartz on August 13, 2008, 11:20:21 PM
i just hate when someone comes up with this kind of ridicously simple solutions..makes me feel dumb!!!!

sebastian...la cagai pa seco!!! maestro!!!  ;D

Hola Daniel.
Don't worry, when Mark Hammer came up with the SWTC I felt dumb too.
You are "seco" too. You've done a terrific job with those hot rod dual rectos and valve amps!

:icon_redface: :icon_redface: thanks.. although my approach is a bit more amateur-ish, all this "Ids, Igs, Zdgs, Abc, tick tack toe" still hits me in the face, and makes me think "what the heck..i´m going for the parlor trick!!"

about the discussion about technical info v/s "tricks":

My POV is that knowledge is a tool, sometimes you don´t need special tools for some jobs, you can make it work with a wrench, a screwdriver and a pair of scissors. The need for more sofisticated tools grows when we start to feel that the basic tools are not enough to get us where we want to go. If we are getting what we want with what we have.. Great!! why bother getting better tools?..Some people, anyway, are more interested in tools, wich is great, they strech the boundaries and produce new, better tools.

But the real wisdom is "how" we use those tools..some people can make marvels with just a wrench.. others need special tools for the same job, both are valid, but the investment is different

Thanks for the cool innovation, Sebastian, and for clearing the air. I just want to point out that where this came up was in a thread about using the Tillman preamp as a booster, so in that context the issue of comparing jfet z-out to tube z-out is moot, and variation in output impedance caused by biasing certainly does affect the usefulness and predictability of the circuit in real-world applications. Of course, you seem to have addressed that problem now.

CCS really does seem to be a woefully unexplored area, with a lot of potential upside--and there is plenty of tube pedigree for that.  :)

Ben

The gain change is my  primary argument.

I do not depend on a small trim pot wiper for long term stability .  FWIW If you look at older lambda power supply often the current limit and voltage adjust trims are full size pots with good wipers and resistive track.

Next will there be enough Id?

Next look for the 80's solid state harvard schematic.   Note the source leg.

I don't post circuits I use with fets  I am aware of CC

Then there is input and output headroom.

I think a "good" design for a paint by number build should include a selection process for the fet(s) used.  Fets don't cost that much and you can sort them with simple homemade testers for what is built here.  People select transistors for FFs why not Fets.

When the "designer" posts a fet design maybe post reading like Vgs off and IDSS at a certain voltage of fet(s) they liked.

I am aware of CC I use it in some of my builds, that's why I posted links and posted about the neumann and Oktava circuits and to read the ANs.  "Designers" need to make the next step IMO.

In answer to Doug's 5th post in this thread:

JFETs just have too much spread to try to pretend to find a trimless way of biasing ANY device in a given family.  For instance, a J201 may have a VgsOFF from -0.3 to -1.5 according to the datasheet, covering a 1:5 ratio.  There is no practical way of squeezing the lowest gain device so as to have as much gain as the highest gain device in the family. So, if uniform gain is a design goal one has to accept that gain will have to be leveled downwards.  Regarding Siliconix AN102, gain is leveled and the drain is properly biased, but other aspects of are sacrificed in the process, such as the simmetry and output dynamic range, which when used as a clipping device does have an audible effect.  Also, as the operating point in terms of the percentage of IDSS varies widely according to the device in use, the resulting harmonic structure is different also, which also makes an audible difference.  I have verified this in several simulations including vendor supplied models and JFET models adjusted for given values of VgsOFF and IDSS.  Of course AN102 method is excellent for general audio applications and for mass production, but for guitar audio I'd still rather have trimpots.

To complement the above, I'm not a fan of source bypass capacitors in JFETs. Yes, they do help to get more gain out from a particular stage, but at the same time they increase the 2nd harmonic content to a point where it becomes too noticeable for my personal taste.  In other words, the square-law (or approximately square-law) of the JFET becomes "too evident" due to the reduced voltage feedback via the source resistor.  I can support this last statement with many many listening tests at the breadboard--and I don't consider myself a golden ear, so if I can notice the differences it's beacause they are pretty evident!  Of course the cathode bypass capacitors in a valve stage are another story, since valves follow a milder three-halves current transfer law which is more bening in terms of  the harmonics that are introduced when the triode is running in the "linear" region.  Bottom line here is that a JFET behaves more like a triode in terms of the harmonics produced when it doesn't have a source bypass capacitor, and this is the essence of the Fetzer Valve.

As some may have noticed, the "revised" ROG circuits have been following such trend.  For instance, when designing Thor no source capactors were used, and circuit values were adjusted by ear to attain the target sound, rather than blindly copying the amp's values.  The output filter stage which boosts bass and cuts highs with a steeper 2nd order slope was tailored specifically to achieve the intended goal, yet it has nothing to do with the amp schematic, but rather to a desired functionality: emulating the 4x12 resonant peak and filtering highs.

Then again, when working on the Supreaux Deux (S.D.) no source bypass capacitors were used and the supply voltage was increased to for more gain and improved dynamic response. The high frequency filtering in the original Supreaux (after 1st stage and 2nd stages) didn't match that of the amp because the output impedance of the triodes was an integral part of the circuit, yet it was not considered.  We did extensive simulations and breadboard experiments to determine the actual operating impedances and cutoff frequencies.  As a result, resistors in series with the drain outputs were included to match the frequency response, however we still deviated from the original tone capacitor value (1n5 instead of 5n) based on what sounded better for our ears.  Now the S.D. sounds much closer compared with the real amp, but of course JFETs and triodes will never be the same, so there is no claim in that respect :icon_wink:

Regarding the AC30 Sim, the author is Stephen Möeller (hope I spelled it right).  He certainly did a great job making a repeatable stage-by-stage opamp implementation of an AC-30 by copying the transient response derived from a sinusoidal burst with exponential decay.  I understand he licensed his design, but I am not aware of a commercial product derived from it.

Sebastian, I read your "new and improved Fetzer valve" article.

Where do these two equations come from?

QuoteVd = 0.6*Vcc + 0.7*|Vp|

Rd = 0.9 * (Vcc - 2*|Vp|) / Idss

In particular I don't see where the .6 and .7 coefficients come from in the first equation.

For the idiots among us, please can someone explain how Sebastian's method keeps the output impedance constant?

I think I understand how the portion of the trimmer between the drain and vcc affects the output impedance, because assuming vcc is at AC ground then it's basically a resistor to ground, which I can get my head round, or is that wrong?
I can't figure out how this interacts with the portion between the drain and the output to keep the impedance constant though. I've tried visualising it taking into account the input impedance of a following circuit, but that doesn't help.
Do you have to factor in the effective resistance/impedance of the fet and source resistor or something?

I've obviously got a big hole in my knowledge, I'd be grateful if someone could fill it, or at least give me some pointers :)

Hmmm... At one end of the trimpot's rotation, R_DS + RS are in parallel with RD; at the other end they are shorted out (w/re. output) and you have only RD. Is that right? If so, count me among the idiots (a place where I feel entirely comfortable  ;D).

Quote from: slacker on August 14, 2008, 01:00:53 PM
For the idiots among us, please can someone explain how Sebastian's method keeps the output impedance constant?

I think I understand how the portion of the trimmer between the drain and vcc affects the output impedance, because assuming vcc is at AC ground then it's basically a resistor to ground, which I can get my head round, or is that wrong?
I can't figure out how this interacts with the portion between the drain and the output to keep the impedance constant though. I've tried visualising it taking into account the input impedance of a following circuit, but that doesn't help.
Do you have to factor in the effective resistance/impedance of the fet and source resistor or something?

I've obviously got a big hole in my knowledge, I'd be grateful if someone could fill it, or at least give me some pointers :)

Quote from: Ben N on August 14, 2008, 02:19:41 PM
Hmmm... At one end of the trimpot's rotation, R_DS + RS are in parallel with RD; at the other end they are shorted out (w/re. output) and you have only RD. Is that right? If so, count me among the idiots (a place where I feel entirely comfortable  ;D).

When the JFET is operating in the so-called saturation or constant-current region, the output impedance is equivalent to the resistor installed between the supply and the drain terminal, named RD for this discussion.  This is because the JFET is acting as a current source, and ideal current sources have infinite resistance by definition.  So, this leaves RD with an infinite resistor to GND in place of the JFET, thus equivalent output resistance is just RD.

Disclaimer: In the real world, the equivalent resistance of the JFET is in the order of hundreds to thousands of kilo ohms instead of infinity, but for all practical purposes it is many times larger than RD so it can be disregarded.

Now in relation to the SWDB configuration, consider the trimpot as two resistors connected in series. Let's call RDa the part that acts as the new supply to drain resistor, and RDb the part that goes in series from the drain terminal of the JFET to the output terminal.  From the previous explanation, the impedance at the drain terminal is RDa, and since RDb is in series with it, the total output impedance is RDa+RDb, which is a constant value as RDa and RDb are part of the same trimpot.

Hope it makes sense!

Yes that makes perfect sense, thanks.

What I was doing was looking at the signal on the drain not the output. So I was thinking the impedance would have been RDa || (RDb + the impedance of what ever it was driving) That's why I couldn't see how it was constant.

Quote from: DougH on August 14, 2008, 12:10:14 PM
Sebastian, I read your "new and improved Fetzer valve" article.

Where do these two equations come from?

QuoteVd = 0.6*Vcc + 0.7*|Vp|

Rd = 0.9 * (Vcc - 2*|Vp|) / Idss

In particular I don't see where the .6 and .7 coefficients come from in the first equation.

At the time the revisited Fetzer Valve article was prepared over two years ago, those coefficients were found empirically by simulations with JFETs with different values of VP and IDSS, so as to satisfy the following criteria:

1) RS=0.83*VP/IDSS (according to Danyuk's paper)

2) Drain voltage (output voltage) just reaches 2*VP when input voltage is +VP, which is just the point where the JFET leaves the constant-current region.  Since an input voltage of -VP produces drain current just to become zero, a simmetrical clipping-free input range from -VP to +VP is obtained.

This was further verified in the breadboard using J201's, 2N5457's and MPF102's with different values of VP and IDSS.

Of course this proofs nothing, so now I also have the full mathematical derivation of the equations that allow determining said coefficients for ANY biasing point, not just RS=0.83*VP/IDSS, where the quiescent drain current is expressed in terms of a percentage of IDSS.

We are about to release an article at the 'groove site with all the math behind. It is currently in the revision stage.

As this appears to be most likely directed at me, I will 'arrogantly' assume that the gauntlet has been tossed and skip the niceties entirely:

- 'Arrogance' is showing an unwarranted importance out of overbearing pride. How can stating a proven scientific fact, no matter how forcefully, be 'arrogant'? The CORRECT use would be to say that it is arrogant to assume that because what you are doing 'works', according to your own definition of 'works', it supersedes proven scientific fact.

- I never called a trimmer on the drain a 'parlor trick', I called it wrong. No need for 'marketing' any other version in when compared to that.

- How do you know a drain trimmer 'does the job' in a circuit, if by simply adjusting it you completely change the circuit's 'job' entirely?? In fact, with each twist of the trim you change the entire circuit itself.

- JFETs don't follow a strict 'square-law'. See Shockley's proof. The 'square-law' just happens to be a good approximation. This goes even more so for short channel JFETs like the J201. A MPF102 is probably closer to a square law approximation than any other of the 'common' JFET types normally used in FX.

- Qualifying designs through limiting the operation of the JFET, and the subsequent formulas used, to only the saturation region is convenient, but is simply not in the slightest bit realistic for our purposes. Unless a JFET stage is used EXCLUSIVELY to be as 'clean' a boost as possible, which, as we are talking about JFETs used in distortion circuits, ain't the case, one HAS TO consider the operation of the JFET in the ohmic region. To ignore this is to limit one's study of the distortion created in a JFET to the hard clip that occurs against the source resistor and completely ignores the 'squashing' that occurs when the signal causes the JFET to operate in the ohmic region - in my opinion the entire raison d'etre for using JFETs in the first place - why the hell else deal with the characteristic spreads that are at the core of this entire 'discussion' and the nightmare that is JFET design?

- Changing the resistance in the drain changes the gain of the stage. Period. I couldn't care less what the value of the trim actually is - though the end user certainly will as it is one entire half of the gain equation (Av=gm*Rd; Rs bypassed); and as JFETs vary so much, it is virtually guaranteed that in order to get the same voltage on the drain as that stated in the original design, the trim will have to have different values for separate, but conceptually identical, circuits. Therefore the gain of the circuit built by the designer will almost assuredly be quite different from the gain of another stage built by someone else, even though they are using the same part number and the exact same circuit. Put it this way - if it so happens that they DO match and the values are the EXACT same for the same bias condition in each case, that's the day someone needs to buy a damn lottery ticket.

- Setting Vgs to that suggested in the Fetzer Valve article to achieve the triode 'three-halves' transfer curve is great - until you apply a signal at the gate and completely change the bias relationship that got you to the three-halves situation in the first place. Because it is set to operate in the saturation region, and never in the ohmic region, Id is controlled exclusively by Vgs, Vds has little to no effect. Because of this, the standard Vgs vs. Id transfer curve (instead of the Vds vs. Id with plots for varying Vgs) is the relationship between Vgs and Id. So unless the coefficients presented are able to physically change the transfer curve, you still have the same JFET transfer curve, not a triode transfer curve, and still have a JFET amplifier. Also, even if Danyuk's paper is entirely correct, and everything works exactly as stated, all that is achieved is a linearly operated JFET simulating a linearly operated triode - which may be great for those hi-fi folks still hanging on the tubes but sick of getting shocked, but it is absolutely useless to a guitarist seaching for even the minimum amount of distortion - at some point, the signal HAS TO clip, or at the very least enter the ohmic region, for that type of distortion to occur, and it is at that exact point the entire reason for setting up the bias according to Danyuk is nullified.

- I never advocated a trimmer on the source, in fact, I never advocated anything except that a trim in the drain to adjust the quiescent drain voltage is wrong.

- One difference between this 'parlor trick' and the standard drain trim 'parlor trick' (please note that these are not my words or phrases, I'm using them for continuity) is that in this situation, unless the resistance of the trim is maxxed, you are immediately adding noise through series resistance, as well as attenuating the signal through voltage division between the portion of the trim from the wiper to the load and the load itself - the signal passed to the next stage, no matter what that stage is, occurs at the juncture between the two. Admittedly, if the load is high, such as a buffer or another FET stage, the attenuation is small, but the added noise won't go away. If the next stage is a BJT common emitter amplifier, chances are, there will be a fair amount of attenuation in addition to the noise, with the end result being a reduction in the S/N ratio even if any loss of gain is made up by the BJT stage.

- The portion of the trim between the wiper and the load adds to the load, being in series with the load, changing the effective drain resistance as the two together (the resistance from the wiper to the load and the load itself) are in parallel with the portion from the wiper to V+. So in this case not only are you changing Rd, the physical resistance between Vdd and the drain, but you are also changing the effective load on the stage at the same time, which also changes the effective drain resistance. This also limits the JFET stage's ability to charge and discharge any following stage's Miller capacitance reducing the frequency response and changing the way the following stage reacts to clipping - which will be slightly different at every setting of the trim and therefore another variable has been added, making the circuit even harder to replicate.

- The way to properly bias a JFET stage from a single voltage supply while keeping the gain structure as replicatable as possible is via Vgs - and there is a very old 'parlor trick' that does just that with a minimal amount of fuss. Biasing via Vgs does introduce the mirror issue of differences in gm from JFET to JFET, which are at the heart of the variation between single JFETs. However, the effect of gm variation between JFETs of the same type is less than that of physically varying a multiple kiloohm Rd, all other things being equal. Nothing is going to be perfect, especially with JFETs, or, as R.G. said, we would see a lot more JFET based consumer equipment.

Regards,

Jay Doyle

It seems like ...and I'm probably wrong about this... but this seems like a variation on the same theme. To me, the best time to use a trimmer is when you are looking to vary the bias (after the circuit is complete) ...and since, to my knowledge, jfets aren't really temperature dependent, isn't it a better solution to find the operating point you want for the jfet and just bias it with fixed resistors ? I posted a self biasing 18v jfet booster in another thread that, because of the way it's set up, works with a large variety of jfets....and no one noticed. Not a peep. It was a Marston circuit, and thats one guy who knows more about jfets than the average EE, so I would make the safe assumption that it is a good circuit. To me, trimmers are GREAT for using on a breadboard to find your bias points and test where you actually want the jfets voltages to be, but past that point a fixed resistor will stay accurate, not be as prone to damage, voltage drift, etc.

I dont know...I should probably just shut up and let the smart guys debate it... :D

Andy
That schematic you posted uses a voltage divider and then a large resistor from the junction to set the impedance.
Can you use that divider for more than one FET stage adding a resistor from the bias junction similar to opamp biasing (Vref) etc?
And I assume adding a cap from the divider to ground would help?
Any examples of this around. I haven't seen any....

John

>- I never advocated a trimmer on the source, in fact, I never advocated anything except that a trim in the drain to adjust the quiescent drain voltage is wrong.

So Jay, what should the hobbyist do? OK, so it's wrong. So almost all the schematics posted are wrong. Now what?

We got it. It's wrong. So what do we do with this? My pedals that I like are "wrong". Am I supposed to fix them? Am I supposed to not post another circuit with a JFET in it until I can figure out how to fix the problem?

This can go on and on. Tolerances have affect a circuit a lot too. No one (that I know) measures the capacitors and resistors and indicates their exact values on schematics. To be as accurate as possible, I would assume we need to do this too. In fact, values of capacitors might be just as important as any other variable. How about pots???? Ever measure them? They are all over the place.

What is everyone here trying to say?

Aron

Dragonfly
If it is the one in the members section.  I noticed it it looks like right out of AN102  a mix of self bias and fixed bias,  Google MK219 oktava schematic you might like this gain stage.  Look for the harvard schematic.

  When you increase voltage make sure to note what happens with greater drain to gate voltage differences.

Aron
what I am trying to say for 9VDC  "paint by numbers" Fet builds for beginners selecting the FET before using it might help to make the effects more repeatable.

  Neumann u87 and KM8x microphones use a self bias with a cap bypassed selected source R: however I like to select fets in a range for that type circuit.

Quote from: JDoyle on August 14, 2008, 06:41:19 PM
As this appears to be most likely directed at me...

Not at all.

Quote from: JDoyle on August 14, 2008, 06:41:19 PM
- I never called a trimmer on the drain a 'parlor trick'...

No one said or implied you did.

Quote from: JDoyle on August 14, 2008, 06:41:19 PM
- How do you know a drain trimmer 'does the job' in a circuit, if by simply adjusting it you completely change the circuit's 'job' entirely?? In fact, with each twist of the trim you change the entire circuit itself.

The same occurs with a source trimmer, only to a worse extent.

Quote from: JDoyle on August 14, 2008, 06:41:19 PM
- JFETs don't follow a strict 'square-law'. See Shockley's proof. The 'square-law' just happens to be a good approximation. This goes even more so for short channel JFETs like the J201. A MPF102 is probably closer to a square law approximation than any other of the 'common' JFET types normally used in FX.

Yes, the square law is an approximation, yet it still allows you to model, predict and study the behavior of a JFET circuit with reasonable accuracy.  In fact, the use of approximate math models and linearization around an operating point are engineering techniques that have been used successfully in many disciplines for decades, if not centuries.  The fact that it is not perfect down to the microvolt doesn't invalidate the analysis at all, and it is not really necessary to have better accuracy just to estimate an operating point and the general behavior of the stage.

Quote from: JDoyle on August 14, 2008, 06:41:19 PM
- Qualifying designs through limiting the operation of the JFET, and the subsequent formulas used, to only the saturation region is convenient, but is simply not in the slightest bit realistic for our purposes. Unless a JFET stage is used EXCLUSIVELY to be as 'clean' a boost as possible, which, as we are talking about JFETs used in distortion circuits, ain't the case, one HAS TO consider the operation of the JFET in the ohmic region. To ignore this is to limit one's study of the distortion created in a JFET to the hard clip that occurs against the source resistor and completely ignores the 'squashing' that occurs when the signal causes the JFET to operate in the ohmic region - in my opinion the entire raison d'etre for using JFETs in the first place - why the hell else deal with the characteristic spreads that are at the core of this entire 'discussion' and the nightmare that is JFET design?

I disagree here for two reasons:
1) The ohmic region is very narrow in comparison to the total output.  For instance, when using a J201 the ohmic region extends just for about VP, i.e roughly when the drain voltage varies from 2*VP down to VP.  So, for an 18V powered circuit like the Supreaux Deux, the ohmic region extends for about 0.8V of the maximum 16.4V of constant-current output range.
2) Typical JFET circuits have two, three or four gain stages.  It is very rare that all stages are clipping.  In fact, the first stage rarely clips, and as the signal fades more and more stages quit clipping, until the last stage runs out of enough signal to clip.  So, you have for most of the time one or more stages entirely within the constant-current region.  Harmonic content, especially 2nd harmonic determines the duty cycle for the subsequent stages that go into clipping.  They are important to the overall sound.  It is the biasing point that determines when the input signal will reach clipping, and also if clipping will occur on both sides simultaneously or on the positive or negative peak first. This does affect sound.

Quote from: JDoyle on August 14, 2008, 06:41:19 PM
- Changing the resistance in the drain changes the gain of the stage. Period.

Entirely true.  However it is equally true that changing the source resistor (RS) affects the JFET transconductance (gm), whether the source resistor is bypassed or not.  And since gain can be expressed as Av= gm*RD, it does depend on RS by means of gm.  This is the crux of my initial post.  RS does vary gain also.  To what extent?  To the same extent as varying RD, as unbelievable as it sounds.

I used three J201's: specimen A with Vp=0.5V and Idss=0.1mA, specimen B with Vp=0.8V and Idss=0.24mA, and specimen C with Vp=1.2V and Idss=0.4mA.  They are pretty representative of low, medium and high VP's.

First, I biased the three JFETs according to the Fetzer Valve values using RS equal to the recommended value for the middle device (1100 ohms), and tuned the drain trimmer to the recommended drain values of 6200, 10900 and 22000 ohms.  Gains obtained were: 10, 14 and 19 dB, respectively. 

Second, I changed the drain resistor for the recommended value for the middle device (10900 ohms), and tuned the source trimmer so as to obtain the recommended drain voltage (same as in the first part).  Required source trimmer values were: 2430, 1100 and 180 ohms, respectively.  And gains obtained were again 10, 14 and 19, respectively.  Decimal differences were less than 0.5 dB with respect to the previous case.

Conclusion: tuning with a drain or source trimmer under similar conditions in a controlled experiment produced the very same gains.  In each case the target drain voltage was chosen for maximum dynamic range according to the particular VP of each stage.

Moreover, drain trimmer resistor required only a 3:1 variation, while the source resistor required a 13:1 variation.  Imagine trying to accurately set 180 ohms for the last stage using a 5k source trimpot.  Very difficult indeed.

And not content with the above, I run the FFT analysis on each case, feeding each stage with its maximum clipping-free input signal, i.e. +/-VP.  The results showed that the 2nd harmonic in the drain trimmer case varied from 11.5% to 12% to 13.8%, while in case of the source trimmer it varied from 8.3% to 12% to 20.3% for the three specimens under test.  It is evident that the source trimmer affects greatly the 2nd harmonic and thus produces a much wider variation in sound than drain trimmer.

Based on all the above, I only see disadvantages in using a source trimmer over a drain trimmer.

I'm open to explore the subject on a respectful and collaborative basis, but I won't debate any more unless solid facts or evidence are presented, such as a simulation, practical measurements, a mathematical model, or a paper.  Each of these posts takes me over an hour, apart from the simulation/breadboard time to gather actual facts before posting, and I also have to think and write in a foreign language.  Time is too short for me lately, so I have to divide myself between work, family, DIY and sleeping hours as efficeintly as possible.

Best Regards,

Sebastian.

Quote from: Gus on August 14, 2008, 10:39:15 PM
Google MK219 oktava schematic you might like this gain stage.
Look for the harvard schematic.

I haven't succeeded finding any of these.  No mic schematic found.  Also, looking for the Fender Harvard only led me to two versions of the valve amps (6G10 and 5F10 models).  If adding solid-state to the search I just found solid-state units for sale or HC reviews.

Could someone post a link if you find a schem, please?

>what I am trying to say for 9VDC  "paint by numbers" Fet builds for beginners selecting the FET before using it might help to make the effects more repeatable.

Sounds like a good idea to me Gus. Thanks for clarifying!

Thanks everyone for expressing their point of view. This has been a good thread. I now understand a large part of it. Thanks Sebastian, your post was very clear to me.

I found the mic schematic (http://www.xaudia.com/omnip/Mics/MicSchLib/OktavaMK219.jpg) on this page (http://recordinghacks.com/microphones/Oktava/MK-219).

Maybe someone with a lot of time and energy (i.e. not myself) on their hands could design a simple JFET-selecting circuit which could easily tell you this JFET should be used in that effect, that JFET should only be used as a switch, etc.  Something a "noob" could put on the breadboard or perf easily, with a socket for the JFET and points at which to hook up a voltmeter?

QuoteI used three J201's: specimen A with Vp=0.5V and Idss=0.1mA, specimen B with Vp=0.8V and Idss=0.24mA, and specimen C with Vp=1.2V and Idss=0.4mA.  They are pretty representative of low, medium and high VP's.

First, I biased the three JFETs according to the Fetzer Valve values using RS equal to the recommended value for the middle device (1100 ohms), and tuned the drain trimmer to the recommended drain values of 6200, 10900 and 22000 ohms.  Gains obtained were: 10, 14 and 19 dB, respectively.

Second, I changed the drain resistor for the recommended value for the middle device (10900 ohms), and tuned the source trimmer so as to obtain the recommended drain voltage (same as in the first part).  Required source trimmer values were: 2430, 1100 and 180 ohms, respectively.  And gains obtained were again 10, 14 and 19, respectively.  Decimal differences were less than 0.5 dB with respect to the previous case.

Sebastian, did you use a bypass cap on the source in this experiment?

earthtoneaudio

 Look at the geofex fet matcher and read my post about IDSS measuring.  This simple two sample should help to select fets if the same brand.  It will be important that the forum adopts a standard way to do this to make sure it can be repeatable.  

this looks good

http://www.forsselltech.com/downloads/schematics/JFET%20Jig1.pdf

EDIT I should add when I posted paint by numbers I meant it in a good way.  That is one way to start to learn.  A fet circuit for a beginner could discourage them.  Until people started posting about transistors for FFs and ways to match and measure a beginner building a FF could have problems.  That is one reason I made the npn boost little or no selection needed for the transistor most small signal Si NPNs should work.

In the oktava circuit look at the mix of self bias and fixed bias and the two resistors in the source leg one not bypassed for a mix of bias and gain control.  In different 219s there are two numbers written on the transformer they are the two  Rs selected for the fet used.  I am guessing the fet is measured and a look up table or formula is used to select the resistors.

Quote from: aron on August 15, 2008, 01:36:41 AM
>what I am trying to say for 9VDC  "paint by numbers" Fet builds for beginners selecting the FET before using it might help to make the effects more repeatable.

Sounds like a good idea to me Gus. Thanks for clarifying!

Aron, I think what needs to happen is we need to establish some criteria for pre-selecting the FETs. This could be like schematics where people note recommended hfe for bjt xsistors and so forth. I agree with Gus that especially for hobby building that specifying a selection criteria for the device is the easiest way to go. Then the designs can just use fixed resistors and etc.

Quote from: stm on August 14, 2008, 11:21:46 PM

Quote from: JDoyle on August 14, 2008, 06:41:19 PM
As this appears to be most likely directed at me...

Not at all.

Quote from: JDoyle on August 14, 2008, 06:41:19 PM
- I never called a trimmer on the drain a 'parlor trick'...

No one said or implied you did.

Jay, it was aimed at me and I answered that in my first post.

Let's just drop it...

Quote from: DougH on August 15, 2008, 09:30:04 AM

QuoteI used three J201's: specimen A with Vp=0.5V and Idss=0.1mA, specimen B with Vp=0.8V and Idss=0.24mA, and specimen C with Vp=1.2V and Idss=0.4mA.  They are pretty representative of low, medium and high VP's.

First, I biased the three JFETs according to the Fetzer Valve values using RS equal to the recommended value for the middle device (1100 ohms), and tuned the drain trimmer to the recommended drain values of 6200, 10900 and 22000 ohms.  Gains obtained were: 10, 14 and 19 dB, respectively.

Second, I changed the drain resistor for the recommended value for the middle device (10900 ohms), and tuned the source trimmer so as to obtain the recommended drain voltage (same as in the first part).  Required source trimmer values were: 2430, 1100 and 180 ohms, respectively.  And gains obtained were again 10, 14 and 19, respectively.  Decimal differences were less than 0.5 dB with respect to the previous case.

Sebastian, did you use a bypass cap on the source in this experiment?

Hi Doug.  These experiments were done WITHOUT source bypass capacitors for the following reasons, as this corresponded to Fetzer Valve case, and because I knew the maximum clipping free input range (+/- VP) and optimum drain biasing voltage, so I could make a fair comparison.

Now I have advanced more in the math analysis of the JFET circuit, and I hope soon I'll be able to calculate the optimal biasing point for the bypassed case (maybe it's the same?), and the maximum input voltage range.

So far now I can provide formulas for the gain for both the unbypassed and bypassed case.  Notice the direct dependence of gain with respect to RD, and a nonlinear dependence with respect to RS (since it is included also in the square root term):

(http://runoffgroove.com/images/attachments/JFET_Gain.png)

It is interesting to notice that now it is possible to calculate the gain increase you get in a particular stage when adding the source bypass capacitor.  As it can be seen, it depends on the source resistor, which in turn sets the operating point.

Example 1: what would be the gain obtained without source bypass for a J201 with VP=0.8 V, IDSS=0.6 mA, RS=1100 ohms and RD=10000 ohms?
Substituting in the first equation we get a value of 4.7 times, or 13.4 dB.

Example 2: what would be the increase in gain if adding a source bypass capacitor in the previous example?  Substituting the values in the third equation gives 2.07 times or 6.3 dB more gain when adding the source bypass capacitor.  Thus, final stage gain would be 13.4+6.3 = 19.7 dB.

Sebastian,

The reason I was asking about whether you used a source bypass cap is because in your experiment where you compared gains by varying the size of the source resistor, you didn't take into account the degenerative feedback that the resistor contributes. And yes, that will make the gain vary quite a bit depending on that resistor size.

I'll have to digest your equations a little later when I have more time.

Thanks for taking the time to post the equations and the results of the work you did.

Doug

Quote from: DougH on August 15, 2008, 10:41:46 AM
The reason I was asking about whether you used a source bypass cap is because in your experiment where you compared gains by varying the size of the source resistor, you didn't take into account the degenerative feedback that the resistor contributes. And yes, that will make the gain vary quite a bit depending on that resistor size.

Both the simulation (done using Microcap 7 for Transient and AC Analysis) and the algebraic analysis do include the effect of the degenerative feedback introduced by RS.  Proof of this is that the gain equations do include the RS term in the denominator, and as RS increases gain reduces by virtue of the degenerative feedback.

Quote from: DougH on August 15, 2008, 10:41:46 AM
I'll have to digest your equations a little later when I have more time.

When the complete analysis is posted, the assumptions and derivation of the equations will be included.  This should allow proper review of the whole process.

Quote from: DougH on August 15, 2008, 10:41:46 AM
Thanks for talkng the time to post the equations and the results of the work you did.

Your welcome.

Sebastian

>Aron, I think what needs to happen is we need to establish some criteria for pre-selecting the FETs. This could be like schematics where people note recommended hfe for bjt xsistors and so forth.

That's great.

Now how far are we going to take this? Are we going to insist that people measure their caps and posts and resistors BEFORE posting so that people can get repeatable results? How about cap types and brands since it does make a difference and the differences can be quite striking?

Where do we draw the line. It's like notation - not even close really.

Aron

Am I just assuming things here, or is all this discussion solely based on the common source amplifier configuration? 

Do common drain/source follower and common gate configurations suffer from the same problems having to do with device variations?

Quote from: Dragonfly on August 14, 2008, 08:55:33 PM
I posted a self biasing 18v jfet booster in another thread that, because of the way it's set up, works with a large variety of jfets....and no one noticed.
I dont know...I should probably just shut up and let the smart guys debate it... :D

What ?  :icon_lol:
You're funny Andrew.
You posted that schematic with no comments.  I was just starting to read the app. notes. ...
What can you say when a cowboy draw his six-shooter faster than his shadow...

Quote from: aron on August 15, 2008, 04:07:49 PM
>Aron, I think what needs to happen is we need to establish some criteria for pre-selecting the FETs. This could be like schematics where people note recommended hfe for bjt xsistors and so forth.

That's great.

Now how far are we going to take this? Are we going to insist that people measure their caps and posts and resistors BEFORE posting so that people can get repeatable results? How about cap types and brands since it does make a difference and the differences can be quite striking?

Where do we draw the line. It's like notation - not even close really.

Aron

Aron, I think the ideas expressed by Gus and Doug about accompanying schematics with JFET values and pre-screening JFETs when building the circuit represent a good compromise solution to JFET variation.  Pretending that ANY JFET in a given family should work *optimally* in a given circuit is asking too much, at least with the current knowledge and understanding of JFETs.

The latest circuits at ROG (Thor, Supreaux Deux) have been designed using "average" JFETs, according to the values in the table shown in Section 11 of the Fetzer Valve article in an attempt to maximize the probability of success for the builder.  But there is still room for trouble if a particular JFET is too far apart from the "average" value of its family.  This is where the proposed screening would enter: by including in the schems the range of values for VP and IDSS where the circuit is intended to work as expected, for each different type of JFET.  So, the builder would have to verify if the JFETs being used complies or not with the requirements using a simple JFET tester.

I don't think the above would allow avoiding trimmers, but at least it would make results far more predictable.

---------------------

Regarding your concern about extending this screening procedure or requirement to other components such as capacitors, I think that would be much over the top.  I'll venture to speak like Mark Hammer and give a metaphor to illustrate this:  properly choosing a JFET would be like the process of making wine, where the JFET spread would mean getting grape juice, wine or vinegar.  We just want wine.  Choosing different cap types, or even CC resistors v/s metalfilms would be more like using Carmenere, Cabernet Sauvignon or Merlot grapes; inevitably some people will prefer one or the other, but they all produce red wine in the end.

Quote from: stm on August 15, 2008, 05:01:41 PM

Quote from: aron on August 15, 2008, 04:07:49 PM

Where do we draw the line.

Aron

---------------------

There ?  Was that conscious ?

>I don't think the above would allow avoiding trimmers, but at least it would make results far more predictable.

Now my question is, what started this? Was there a rash of people complaining about their JFET projects any more than people complaining about Fuzz Face issues? Just wondering. As much as a "hack" the drain trimmer was, it allowed me to create many JFET projects with good results. When I built 2 or 3 op amp projects, they still sounded different from each other (no doubt due to caps and pot variation I assume). I do remember problems a while ago with the old MPF102 and even some J201, but with the Fairchild and Siliconix, the large variations have long gone for me in terms of getting a JFET sounding circuit to sound good.

Quote from: aron on August 15, 2008, 04:07:49 PM
>Aron, I think what needs to happen is we need to establish some criteria for pre-selecting the FETs. This could be like schematics where people note recommended hfe for bjt xsistors and so forth.

That's great.

Now how far are we going to take this? Are we going to insist that people measure their caps and posts and resistors BEFORE posting so that people can get repeatable results? How about cap types and brands since it does make a difference and the differences can be quite striking?

Where do we draw the line. It's like notation - not even close really.

Aron

Actually, it's not a bad idea to measure resistors before building, even though I don't do it. I hear amp guys insist all the time that you measure resistors before installing, due to the possibility of reading color codes incorrectly, tolerances, etc.

To me, the point of specifying criteria for a JFET is to basically get the circuit to bias up correctly. Then you could build the circuit with fixed resistors and it would pretty easy to get circuits that consistently work. It would also make the gain of the circuit consistent across builds. Cap types and so forth I view as a secondary "taste" consideration.

Quote from: aron on August 15, 2008, 08:04:44 PM
>I don't think the above would allow avoiding trimmers, but at least it would make results far more predictable.

Now my question is, what started this? Was there a rash of people complaining about their JFET projects any more than people complaining about Fuzz Face issues? Just wondering. As much as a "hack" the drain trimmer was, it allowed me to create many JFET projects with good results. When I built 2 or 3 op amp projects, they still sounded different from each other (no doubt due to caps and pot variation I assume). I do remember problems a while ago with the old MPF102 and even some J201, but with the Fairchild and Siliconix, the large variations have long gone for me in terms of getting a JFET sounding circuit to sound good.

I think what started it was people recognizing that there's probably a better way of doing this so hey, let's explore it.

>I think what started it was people recognizing that there's probably a better way of doing this so hey, let's explore it.

Now that is _cool_. But I cannot help but think that for some reason this discussion got a lot more heated and debated than something like stacked transistors or stacked op amps.

In any case, a LOT of useful info was posted IMO.

We have updated the JFET Tester in a Fetzer Valve article with a more user-friendly version that is simple to build as a tool for measuring IDSS and VP fast and easy by flipping an SPDT switch.

http://runoffgroove.com/fetzervalve.html#11

  That's enough to make me want to build the tester, and figure out the power supply and then build around some Jfets !.
 

Cool! thanks for the work on this.

john

Great ! Thanks !

I think this thread was a good one.

Quote from: stm on August 15, 2008, 12:25:56 PM

Quote from: DougH on August 15, 2008, 10:41:46 AM
The reason I was asking about whether you used a source bypass cap is because in your experiment where you compared gains by varying the size of the source resistor, you didn't take into account the degenerative feedback that the resistor contributes. And yes, that will make the gain vary quite a bit depending on that resistor size.

Both the simulation (done using Microcap 7 for Transient and AC Analysis) and the algebraic analysis do include the effect of the degenerative feedback introduced by RS.  Proof of this is that the gain equations do include the RS term in the denominator, and as RS increases gain reduces by virtue of the degenerative feedback.

Well, okay I guess my point is that if you are claiming that varying source resistance in an unbypassed source circuit will affect gain, I agree completely, mainly due to the effect of the degenerative feedback. But are you claiming that varying the source resistance in a bypassed source circuit affects gain as well? It's not clear to me if that's what you are claiming as well.

Varying source resistor WITH or WITHOUT source bypass capacitor changes the gain.

Here I posted the gain formulas for each case:

http://www.diystompboxes.com/smfforum/index.php?topic=70065.msg563089#msg563089

The bypassed gain is higher of course, but it still depends on the quiescent or steady-state DC drain current, which is set solely by RS and the JFET parameters IDSS and VP, as at DC the effect of the bypass capacitor is null.  Then, when signal is applied, the effect of degenerative feedback by means of RS disappears because of the source bypass capacitor, but gain is was already subject to the DC operating point.

I have confirmed this by:

a. Developing the mathematics behind (which lead to the formulas presented in the link above)
b. In simulations
c. In practical circuits at breadboard level.

Best regards,

Sebastian

Of course, changing Rs alters the bias point and with it the gain at that point on the transfer characteristic but it is important to realize that the gain is only constant in the small signal sense.  With Rs bypassed, vgs sees the full input swing and therefore the gain is dynamically varying and with it, adding the characteristic increase in 2nd harmonic distortion. 

alanlan's got it, there's a need to understand why zero-crossing numbers (short-cut math stuff) are replaced by curves in the greater scheme of things ... indeed, in that realm Rs chiefly regulates the harmonics producing transfer curvature of the transconductance stage through the action of local Negative Feedback ... in his paper Dannyuk sets Rs to match the Harmonic Distortion profile of a test triode for his jFET circuit (his goal) while also setting bias current in the process ... note that with higher current you get more noise for one, and as you drop Rs you also lose headroom ...

Vd plays a secondary role in establishing drain current - up to saturation limits of course, and so the same goes of Rd once Id is set by Rs and rough Vd values ... in other words you can spare yourself production head-aches by selecting Rd at a good average value and putting a trimmer at Rs - even if you don't know your likely worse-case Vgs(off) and Idss spreads this will work well for biasing single-ended gain stages with ease ...

for matching and spec'ing there is no choice but to follow a proper Idss & Vgs(off) test and match them to a reference data-pair if predictable results are required - this is even more important in VCR applications because of the super high sensitivity around Vgs(off) ... if you play with these variables carefully you can build a reliable true-schematic emulation of the Fender Vibrato and Tremolo circuits ...

pictures @11

Quote from: Eb7+9 on August 16, 2008, 10:57:35 PM
Vd plays a secondary role in establishing drain current - up to saturation limits of course, and so the same goes of Rd once Id is set by Rs and rough Vd values ... in other words you can spare yourself production head-aches by selecting Rd at a good average value and putting a trimmer at Rs - even if you don't know your likely worse-case Vgs(off) and Idss spreads this will work well for biasing single-ended gain stages with ease ...

It is better to select RS at a good average value and trim RD instead.  If RD is wired as proposed at the beginning of this thread (SWDB method), then output impedance will remain constant.  Link here: http://www.aronnelson.com/gallery/main.php/v/STMs-Circuit-Ideas/SWDB.png.html

I explained before with practical data why tuning RD should be preferred over tuning RS to set the operating, which I reproduce here for clarity:

---------------------------------------------------------------------------
I used three J201's: specimen A with Vp=0.5V and Idss=0.1mA, specimen B with Vp=0.8V and Idss=0.24mA, and specimen C with Vp=1.2V and Idss=0.4mA.  They are pretty representative of low, medium and high VP's.

First, I biased the three JFETs according to the Fetzer Valve values using RS equal to the recommended value for the middle device (1100 ohms), and tuned the drain trimmer to the recommended drain values of 6200, 10900 and 22000 ohms.  Gains obtained were: 10, 14 and 19 dB, respectively.

Second, I changed the drain resistor for the recommended value for the middle device (10900 ohms), and tuned the source trimmer so as to obtain the recommended drain voltage (same as in the first part).  Required source trimmer values were: 2430, 1100 and 180 ohms, respectively.  And gains obtained were again 10, 14 and 19, respectively.  Decimal differences were less than 0.5 dB with respect to the previous case.

Conclusion: tuning with a drain or source trimmer under similar conditions in a controlled experiment produced the very same gains.  In each case the target drain voltage was chosen for maximum dynamic range according to the particular VP of each stage.

Moreover, drain trimmer resistor required only a 3:1 variation, while the source resistor required a 13:1 variation.  Imagine trying to accurately set 180 ohms for the last stage using a 5k source trimpot.  Very difficult indeed.

And not content with the above, I run the FFT analysis on each case, feeding each stage with its maximum clipping-free input signal, i.e. +/-VP.  The results showed that the 2nd harmonic in the drain trimmer case varied from 11.5% to 12% to 13.8%, while in case of the source trimmer it varied from 8.3% to 12% to 20.3% for the three specimens under test.  It is evident that the source trimmer affects greatly the 2nd harmonic and thus produces a much wider variation in sound than drain trimmer.

Based on all the above, I only see disadvantages in using a source trimmer over a drain trimmer.
---------------------------------------------------------------------------

Quote from: alanlan on August 16, 2008, 08:10:52 PM
Of course, changing Rs alters the bias point and with it the gain at that point on the transfer characteristic but it is important to realize that the gain is only constant in the small signal sense.  With Rs bypassed, vgs sees the full input swing and therefore the gain is dynamically varying and with it, adding the characteristic increase in 2nd harmonic distortion. 

That's true. Just want to emphasize that even if the gain varies dynamically for large signals, overall gain is clearly affected by variations in the source resistor, whether with or without source bypass capacitor installed, as demonstrated by the following graph:

(http://i38.tinypic.com/33tihrk.png)

Blue curves correspond to the unbypassed case, and red curves correspond to the bypassed case.  One can readily see the gain increase when adding the bypass capacitor.  Also, the red curves exhibit some noticeable squashing at the tops when compared to the bottoms, which is the effect of the increased 2nd harmonic content.

Quote from: aron on August 15, 2008, 10:06:12 PM
>I think what started it was people recognizing that there's probably a better way of doing this so hey, let's explore it.

Now that is _cool_. But I cannot help but think that for some reason this discussion got a lot more heated and debated than something like stacked transistors or stacked op amps.

I think that had more to do with clashing personalities and attitudes in some other threads.

QuoteJust want to emphasize that even if the gain varies dynamically for large signals, overall gain is clearly affected by variations in the source resistor, whether with or without source bypass capacitor installed, as demonstrated by the following graph:

As I suspected, from your graphs the gain does not appear to vary as much in a circuit that has the source bypassed. But I don't always trust simulations. I'll have to play with this stuff on the breadboard to get a handle on what's going on.

Good info in this thread!

I want to express an idea to see if it rings a bell:  the two *main* JFET parameters that define the response of a particular JFET are the gate cutoff voltage (VP) and the drain saturation current (IDSS).  At first glance one could say we have two degrees of freedom that need to be adjusted in a given circuit, so a *perfect* biasing scheme should require two trimpots (or choosing two resistors).  This is quite evident in the case of the self-bias method where the selection of RS and RD are both relevant to the final circuit behaviour.

Currently we have resorted to using a single trimpot or adjustment for either RS or RD, but as the drain voltage is adjusted, the operating point (in terms of drain current) is changed also, not to speak about gain and input dynamic range.

Further investigation show that for JFETs with the same part number, there is a definite and fixed relation between IDSS and VP.  This can be seen in graphic form in J201 and 2N5457 datasheets (Fairchild manufacturer, 3rd page).  In other words, when a datasheet indicates VP from 0.3 to 1.5, and IDSS from 0.2mA to 1mA, it doesn't mean you can have a JFET with any pair of VP and IDSS values withing those ranges.  These parameters are in fact "tied" by a definite relation, which is approximately IDSS=a*(VP^b), where 'a' and 'b' are constants that correspond to that particular device family.

The above means that there is in fact a single degree of freedom that differentiates one J201 from another. Now the question is, how do we take this to our advantage? The next logical step is to do a thorough analysis on mixed biasing methods, combining both gate voltage and self-bias.

Well, if that's correct, you have just reduced two handles down to one handle.

Now we just have to figure out how to grab hold of it.

Quote from: stm on August 18, 2008, 10:28:44 AM
I want to express an idea to see if it rings a bell:  the two *main* JFET parameters that define the response of a particular JFET are the
Further investigation show that for JFETs with the same part number, there is a definite and fixed relation between IDSS and VP.  This can be seen in graphic form in J201 and 2N5457 datasheets (Fairchild manufacturer, 3rd page).  In other words, when a datasheet indicates VP from 0.3 to 1.5, and IDSS from 0.2mA to 1mA, it doesn't mean you can have a JFET with any pair of VP and IDSS values withing those ranges.  These parameters are in fact "tied" by a definite relation, which is approximately IDSS=a*(VP^b), where 'a' and 'b' are constants that correspond to that particular device family.

number one assumption made going over jFET device data - where the datasheet shows the "typical" Idss-Vgs(off) curve ... this is a middle-of-the-road curve, if the data was properly shown as a Gaussian cloud around that curve it would dissuade people from working with these devices and thus buying them ... a device "lot" is said to be tight when all devices can be assumed to lie very closely together to such a curve ... the assumption that one's lot is tight is what usually leads to serious questioning afterwards in practice ... it would be nice if Vgs(off) and Idss did track but they don't always in general - at least systematically - hence the reason why people test for both parameters ... things possibly can get even worse when devices are not from the same lot, but still within a lot considerable variations exist otherwise ... again, this has a marked impact on VCR applications - a 15%~20% variation in Vgs(off) leads to around x100 variation in max resistance in a swept voltage application (ie., phasors) ...

I think this thread has made me realize who I do and do not want to party with.

:icon_mrgreen:

 

;D ;D ;D ;D ;D ;D ;D ;D ;D

Touche Brian!



john

OK guys, lets try and keep this one on topic since there are some really good technical examples in here.

Quote from: DougH on August 18, 2008, 10:32:31 AM
Well, if that's correct, you have just reduced two handles down to one handle.

Now we just have to figure out how to grab hold of it.

Exactly!

Quote from: Eb7+9 on August 18, 2008, 11:01:51 AM

Quote from: stm on August 18, 2008, 10:28:44 AM
I want to express an idea to see if it rings a bell:  the two *main* JFET parameters that define the response of a particular JFET are the
Further investigation show that for JFETs with the same part number, there is a definite and fixed relation between IDSS and VP.  This can be seen in graphic form in J201 and 2N5457 datasheets (Fairchild manufacturer, 3rd page).  In other words, when a datasheet indicates VP from 0.3 to 1.5, and IDSS from 0.2mA to 1mA, it doesn't mean you can have a JFET with any pair of VP and IDSS values withing those ranges.  These parameters are in fact "tied" by a definite relation, which is approximately IDSS=a*(VP^b), where 'a' and 'b' are constants that correspond to that particular device family.

number one assumption made going over jFET device data - where the datasheet shows the "typical" Idss-Vgs(off) curve ... this is a middle-of-the-road curve, if the data was properly shown as a Gaussian cloud around that curve it would dissuade people from working with these devices and thus buying them ... a device "lot" is said to be tight when all devices can be assumed to lie very closely together to such a curve ... the assumption that one's lot is tight is what usually leads to serious questioning afterwards in practice ... it would be nice if Vgs(off) and Idss did track but they don't always in general - at least systematically - hence the reason why people test for both parameters ... things possibly can get even worse when devices are not from the same lot, but still within a lot considerable variations exist otherwise ... again, this has a marked impact on VCR applications - a 15%~20% variation in Vgs(off) leads to around x100 variation in max resistance in a swept voltage application (ie., phasors) ...

I agree that "typical" curves can be "pretty" versions of reality.  Nevertheless in my experience from the many different JFETs I have measured (J201, PN4392, J111, MPF102, 2N5457, 2N5458) I can confidently say there is a strong correlation between VP and IDSS, in other words, increasing VP means increasing IDSS values.  In fact, this relation appears pretty straight when the IDSS v/s VP graph is log-log, suggesting a power-like relationship.

Even though IDSS values do not fit perfectly to the ideal curve, this dispersion is bounded so it still allows for some useful results.  IME we are talking about +/- 10% variation from the theoretical value.  If we disregard curves entirely, then the hybrid biasing proposed in Siliconix AN-102 should be disregarded as well, as it relies on using typical curves and expected minimum/maximum parameters.

Regarding the use of JFETs as voltage controlled resistors, I agree that VP is the most important parameter to consider for this particular application.  When you match JFETs for VP, then resistance variations due to variations in Rds(on) or VP/IDSS are surprisingly small.

yes, life's one great jFET device theory party ...

if you compare Idss-Vgs(off) data curves for different device types, ie. between manufacturers, you'll find they don't have the same profile or even concavity ... the random variations overall is shown to be process dependent and not wholy systemic on physical principles - this makes sense to me ... log-log domain or not the profile is not linear and therefore the relation is not systemically proportional - otherwise that would be stressed in textbooks ... IME Idss and Vp can vary by factors of several 100% - if you use a match-test method that has NFB in the source circuit then the "test voltage" values you get of course can easily be of the order of 10% provided there's enough NFB ... that's why such test methods are considered bogus and never mentioned in manufacturers app notes - otherwise they'd be ...

Quote
Regarding the use of JFETs as voltage controlled resistors, I agree that VP is the most important parameter to consider for this particular application.  When you match JFETs for VP, then resistance variations due to variations in Rds(on) or VP/IDSS are surprisingly small.

just to be clear minimum Rd is a function of both Idss and Vp - again, IME I've found Rd min variations to exceed factors of 3 or 4 ... it all depends on the devices you have to play with - one might be lucky and be dealing with a tight set but you only really know until you write down your number pairs ... Vp is not most important as far as the benchmark "min" value goes, both variables have near equal weight in that equation ... I'm referring to how the range of controllability is affected by variations in Vp ... this is why phasors only typically traverse through one decade of resistance change and are not typically used for large-valued resistance ranges (this is one area where opto-couplers blow jFETs away) ... and the reason why we see low valued (~20k) shunt resistors across VCR jFETs in phasors ...

when you use a Drain load trimmer to set the bias voltage in the Drain circuit you are not affecting bias current nearly as much as you would if you were trimming the Source resistance ... also, I don't see why output impedance is a big concern in jFET circuits since we're typically looking at a largish resistance level in the successive stage - unless drive impedance plays an important role in the driving the Gate diode when turning it on to produce clipping effects but then again bias trimming in the Drain circuit never involves driving down the load resistor that much across the linear bias range ... in my jFET overdrivers (Meteor and modded versions) I haven't seen any instance of distortion or tone quality change by varying the loads ... I really think that tube-amp-schematic simulations are not biasing jFETs for optimum noise - and I think it has to do with this propensity to bias in the Drain circuits and neglect the potential for achieving similar gain ratings but at lower bias current settings ... again, the app notes make clear that jFETs are known for yielding higher voltage gains at lower bias levels ... the obvious question then is why insist on biasing at higher currents, only to lose some available gain and yield more noise ?

I hate to mention it, but there's an existence theorem in play here.

There have been some decades of Really Smart Guys trying to make JFETs tractable. Guys who live and breath semiconductor physics in the office next to the guys who've designed analog for their entire professional lives, and many such pairs, with big money and professional prestige to be had. If there was a simple underlying principle to get JFETs to behave, it is likely that it would have been found. That doesn't mean it does not exist - but the odds make winning a trifecta seem like a sure thing.

No matter how many (or how wet) pipe dreams you have about designing a priori Fet-for-tube replacements for Fender vibratos and other esoterica, the variations of JFETs from the factory will almost always make you use trimmers, use selective components, or JFET selection.

JFETs vary. Expect it. Roll with it or design around it.

I know everyone's been talking about the class-A common source configuration, but there are other ways of making gain from JFETs...

What about common gate?  If you use it as a current follower you can get voltage gain which is independent of device characteristics.  Then you just slap some source followers on the input and output, which gives you current gain while simultaneously providing good input/output impedances.  If you're willing to add the complexity of two more transistors, you can get power gain without phase inversion which is tolerant of device variations.

I have this on the breadboard right now, and it's proving to be surprisingly easy to tweak, even without coupling capacitors.  Right now it's two MOSFETs followed by one JFET, but I'm working on all-JFET and BJT/Darlington versions next. 

I don't know if anyone would be interested in exploring this more, but if so I can start another thread with some pretty pictures and stuff.

Alex,

Sounds good to me.

I'd be interested to know also, but my first doubt (without any justification really) is that it won't solve the fundamental problem of reliable, reproducible biasing but I'm saying this in the hope that you'll show me the light!

Feel free to start another thread but something else just occurred to me (you've really got the juices flowing on this one):

If you look at a common gate amplifier, the signal is applied to the source and requires a fairly low impedance driver.  OK, fair enough, and the signal on the source modulates vgs  to vary id which can then develop a voltage across a load RL or be fed into a current to voltage convertor etc.

But isn't a common source with Rs very similar i.e. we use the high impedance gate input for our signal which the source then follows (but not with quite unity gain) so there is a vgs signal which modulates id and, well, you know the rest.

So does the common gate really achieve anything useful?

There is no difference to the biasing arrangements whether you use common source, common gate, or common drain. They can all (potentially at least) be done with exactly the same resistance arrangements, only the caps rearranged for input, output, and 'commoning'.

Quote from: alanlan on August 19, 2008, 04:52:08 PM
So does the common gate really achieve anything useful?

common gate, common base, common grid ... are all current followers : low Z-in, high Z-out ... current gain near or equal to unity ... if you look at them from a voltage point of view they won't seem useful ...

Quote from: Eb7+9 on August 19, 2008, 11:00:15 PMlow Z-in, high Z-out ... current gain near or equal to unity ...

???
Did you mean voltage gain?

Quote from: Eb7+9 on August 19, 2008, 11:00:15 PM
common gate, common base, common grid ... are all current followers : low Z-in, high Z-out ... current gain near or equal to unity ... if you look at them from a voltage point of view they won't seem useful ...

The primary use for common gate/base/grid is for power gain at RF with high isolation between input and output. With the control element grounded, there is a much smaller feedback capacitance.

Voltage gain may be large, as may power gain, because of the difference in impedances. It takes quite a small voltage to make a given current flow in the low impedance seen at a BJT emitter-to-base. But that same current happens at what could be very high voltage on the collector.For instance, if you have an NPN set up with base grounded, emitter pulled down by just enough to turn the transistor on, and you then force a 10ma change into the emitter, it may only change the emitter voltage a fraction of a volt. But the collector can be supplied by a couple of hundred volts, and that same current change appears at the collector and across any collector load. So the voltage gain may be large.

The only issues with common-control-element circuits is that the input side is quite difficult to drive in the normal voltage-centric sense because it is quite low impedance.

The next biggest uses of common base/gate/grid is for level shifting and cascoding. You tie the control element to a fixed voltage, then use changes on the emitter/source/cathode to make same-current but much different voltage loads. In cascodes this happens, but the control element can be grounded for AC purposes and fixed for DC purposes. Music Man amps used a 30V JFET as an input amplifier, and cascoded its drain with a tube to keep damaging voltages off the drain of the JFET. The tube took the voltage stress and reflected the signal current to the much higher B+ for the tube.

Quote from: Eb7+9 on August 19, 2008, 11:00:15 PM

Quote from: alanlan on August 19, 2008, 04:52:08 PM
So does the common gate really achieve anything useful?

common gate, common base, common grid ... are all current followers : low Z-in, high Z-out ... current gain near or equal to unity ... if you look at them from a voltage point of view they won't seem useful ...

Yes, I know that but it has been suggested that the common gate is the answer to all our biasing problems, which is what this thread is about.  I'm interested to know how it answers our collective "problem".

I don't mean to make common gate as a panacea for JFET biasing problems, mainly because the amplifier you end up with is quite different from the common source amplifier, and nowhere near a 'class A triode' type of amplifier.   Plus, the prototype on my breadboard right now works, but it doesn't sound good (yet).

That being said, there are a couple ways to bias a common gate amplifier.  You can bias it like a voltage amplifier or as a current follower.  The difference being (as far as I can tell in my reading so far) the size of the source resistor and hence the input impedance.  As Rsource becomes smaller, the circuit acts less like a voltage amplifier and more like a current follower, or something like that... but the real point to making Rsource smaller is that it removes the device coefficients from the gain equation.  Then the voltage gain becomes Rdrain/Rsource (I think I'm remembering that right... I'll have to go back to Wikipedia... :) )

Yes, the obvious problem is the impedance matching.  If only there was a simple buffer circuit which has high Z in and low Z out... Oh yeah, the source follower does that!  You need one at the input so you can plug in a guitar, and one at the output so you can drive whatever might come later in the signal chain. 

The price you pay for splitting the voltage and current gain into different devices brings the tally up to 3 transistors, and if you're clever about biasing you might not need coupling caps between them.  The Rsource for the common gate and the first source follower can be the same resistor, and if you hook up the second source follower like a SRPP output stage, then its source resistor can pull double duty as Rdrain for the common gate stage, and Rsource for the output source follower.  If you make it variable it's a gain control.

New thread with pictures coming up soon, I promise.

Quote from: alanlan on August 20, 2008, 07:44:55 AM

Quote from: Eb7+9 on August 19, 2008, 11:00:15 PM

Quote from: alanlan on August 19, 2008, 04:52:08 PM
So does the common gate really achieve anything useful?

common gate, common base, common grid ... are all current followers : low Z-in, high Z-out ... current gain near or equal to unity ... if you look at them from a voltage point of view they won't seem useful ...

Yes, I know that but it has been suggested that the common gate is the answer to all our biasing problems, which is what this thread is about.  I'm interested to know how it answers our collective "problem".

You're right, alan. The use of common source/drain/gate has almost nothing to do with biasing predictability. It is possible to take the exact same circuit of resistors and JFET, and get all three types of circuit by merely rearranging where the signal comes in and goes out, and which terminal is "grounded" by a cap to ground.

There is nothing inherent in "common-gate-ness" that solves bias issues of itself.

**WARNING: LITERARY ALLUSION**

Quote from: R.G. on August 20, 2008, 09:23:04 AMIt is possible to take the exact same circuit of resistors and JFET, and get all three types of circuit by merely rearranging where the signal comes in and goes out, and which terminal is "grounded" by a cap to ground.

Kinda like the Soldier in White?  (Catch-22)

Quote from: stm on August 18, 2008, 09:33:56 PM

Quote from: DougH on August 18, 2008, 10:32:31 AM
Well, if that's correct, you have just reduced two handles down to one handle.

Now we just have to figure out how to grab hold of it.

Exactly!

And I have found it.  Well, in fact I found two things, really:

1) I found the real story on SOURCE v/s DRAIN trimmers in JFET circuits.  The preferred biasing method is different depending if your source resistor is bypassed by a capacitor or not.

2) I found how to bias a JFET amplifier with a SINGLE trimmer without significant effect on gain, input dynamic range, output impedance, and harmonic content.  This works for both the bypassed and unbypassed cases.

Sebastian,
I know this thread is about source vs. drain trimmer but it can be done without a trimmer.  AN102 works.  I've tried it on a batch of J201s as reported here:

http://www.diystompboxes.com/smfforum/index.php?topic=69885.msg561231#msg561231 (http://www.diystompboxes.com/smfforum/index.php?topic=69885.msg561231#msg561231)

Quote from: alanlan on August 20, 2008, 03:06:47 PM
Sebastian,
I know this thread is about source vs. drain trimmer but it can be done without a trimmer.  AN102 works.  I've tried it on a batch of J201s as reported here:

http://www.diystompboxes.com/smfforum/index.php?topic=69885.msg561231#msg561231 (http://www.diystompboxes.com/smfforum/index.php?topic=69885.msg561231#msg561231)

Hi alanlan,

Last night I gave it a stab and it does work indeed.  I tired it in the sim with three different J201's (with Vp 0.5 V, 0.8V and 1.2V, and IDSS varying accordingly as well).  I got the Vp and Idss values from actual J201's I had, just to be sure I wasn't using nonsense Vp-Idss pairs.

In the end I had very little gain without source bypass capacitor (around 3 dB), so I added a 100u source bypass capacitor and gain boosted a good deal (around 20 dB).  Using a series resistor with said cap allows to establish gain to any desired value in between.  I verified gain didnt vary significantly from device to device, and drain voltage spanned about 1 volt between the minimum and maximum Vp.  I think this is a great alternative when you want to reliably amplify a low level signal with a known gain, as you can totally avoid trimmers.  It is very likely that you would need to set proper values for Rs and Rd depending on each batch, as JFETs from different batches and/or manufacturers could vary a good deal, as pointed before by Eb7+9, but it still works pretty good for what it is.

Regarding "our" use for stompboxes, there were some chareacteristics of the resulting circuit that I didn't like, though:

1) The need for bypassed source resistor added way too much 2nd harmonic distortion for my taste when signals get large.
2) The output dynamic range was greatly reduced (bottom peak at the output clips around 3 to 4 volts above ground, instead of 1 to 1.5V above).
3) Depending on if the device had large or small Vp, the tops or bottoms of the waveform clipped earlier/later, so getting into the clipping region will not be the same.

Based on the above, I prefer using a single trimmer "wisely" for stompbox use.  Indeed, using one trimmer is not bad at all.  In several three-stage JFET circuits you can find some interesting sweet spots by tweaking the biasing of each stage by ear anyway.  This is particularly true now that I've found how to do it for unbypassed source circuit while keeping gain and input dynamic range constant.

http://www.sdiy.org/oid/mics/Oktava-MK219.gif


http://www.sdiy.org/oid/mics/Oktava-MK-319.gif
R3, R4 fixed bias, R7, R8 self bias

R7 and R8 look to be selected for the fet for gain control and bias when you open the microphone you will see two numbers written on the transformer case they are the R 7 and R8 values.  It is a combo of fixed and self bias.  The microphone is powered by 48VDC with two 6.8K matched to pins 2 and 3(google phantom power)

Another thing to look at is the use of a negative supply so you can use a higher value source R to make it a quasi constant current bias, you can find this in books.  You can partial(cap and gain control resistor) or  fully bypass(cap) the source to ground.  This is what is used in the early 80's fender harvard FET preamp.  So make say a +- 15VDC supply and have fun.  It could also be a say +20 and -10 or ......

or a
higher voltage with a
MIX of fixed and self bias.  The fet "feels" only the difference between the fixed and self bias part this allows a greater voltage from source to ground for a quasi constant current HOWEVER one would need to be mindful of the way the circuit powers up.

Quote from: Gus on August 21, 2008, 10:05:53 AM
http://www.sdiy.org/oid/mics/Oktava-MK219.gif
http://www.sdiy.org/oid/mics/Oktava-MK-319.gif
R3, R4 fixed bias, R7, R8 self bias

R7 and R8 look to be selected for the fet for gain control and bias when you open the microphone you will see two numbers written on the transformer case they are the R 7 and R8 values.  It is a combo of fixed and self bias.  The microphone is powered by 48VDC with two 6.8K matched to pins 2 and 3(google phantom power)

Another thing to look at is the use of a negative supply so you can use a higher value source R to make it a quasi constant current bias, you can find this in books.  You can partial(cap and gain control resistor) or  fully bypass(cap) the source to ground.  This is what is used in the early 80's fender harvard FET preamp.  So make say a +- 15VDC supply and have fun.  It could also be a say +20 and -10 or ......

or a higher voltage with a MIX of fixed and self bias.  The fet "feels" only the difference between the fixed and self bias part this allows a greater voltage from source to ground for a quasi constant current HOWEVER one would need to be mindful of the way the circuit powers up.

Thanks for pointing out these schems.  They are good examples of how to use a JFET as a practical preamp.  I find interesting the use of a 50% split source resistor with just one half bypassed: some more gain but not too much.  I wonder if this hides some special property like more stable gain and/or biasing point, reduce harmonic distortion, etc.

I remember having seen a Carvin guitar amp with a JFET preamp input stage.  I don't have it hand, so I don't recall the exact model, but I believe it did use positive and negative supplies as well.  IIRC, it also had CD4049's or the like for the distortion stages.

IME being bound to a single +9V supply prevents from getting the full potential from a given circuit.  Yes, there are tricks to resort to single supply biasing, but low voltage v/s high voltage supplies provide additional benefits like what you mentioned: a more constant-current behaviour for biasing circuits; it also allows opamps to have better output capability and less distortion, apart from increased headroom and dynamic range.  All of these has audible effects.

Regarding the Oktava MK-319 schem, it should be noted that R2 and R5 are kiloohms instead of megaohms. 
EDIT: Gus confirmed the megaohm values as normal for use in mic circuits, so the line above should be disregarded!

Quote from: Gus on August 14, 2008, 10:39:15 PM
Dragonfly
If it is the one in the members section.  I noticed it it looks like right out of AN102  a mix of self bias and fixed bias,  Google MK219 oktava schematic you might like this gain stage.  Look for the harvard schematic.

  When you increase voltage make sure to note what happens with greater drain to gate voltage differences.

Its the one in the Marston article...probably the same as AN102 (id need to look, but it makes sense)...seems like a nice starting point for stable bias on a wide range of Jfets.

I'll check the Oktava schemo ...thanks !

BTW...for those who couldnt locate it, here's the schematic I posted (from Marston/AN102)

(http://img.villagephotos.com/p/2008-1/1294978/JFETAMPLIFIER.GIF)

R2 and R5 are 680megohms and in some condenser microphones up to 3Gig.  You don't want to discharge the charge on the capsule because of the way a condenser microphone like this works.  The values of R7 and R8 are different in different 219s and 319s and don't have to be in a 50/50 ratio like the one that was traced.  I QUESS they measure the fet and use a look up table to select the gain and total bias value.

Quote from: Gus on August 21, 2008, 11:20:56 AM
R2 and R5 are 680megohms and in some condenser microphones up to 3Gig.  You don't want to discharge the charge on the capsule because of the way a condenser microphone like this works.

Oh boy, it's true that one learns something new everyday.  I added a comment in my post above so it won't cause confusion.

Quote from: Gus on August 21, 2008, 11:20:56 AM
The values of R7 and R8 are different in different 219s and 319s and don't have to be in a 50/50 ratio like the one that was traced.  I QUESS they measure the fet and use a look up table to select the gain and total bias value.

I see, it makes sense.

Cool schem, Andy.  Is your circuit intended for J201's or another type of JFET?

Quote from: stm on August 21, 2008, 11:47:53 AM
Cool schem, Andy.  Is your circuit intended for J201's or another type of JFET?

Its straight from the Marston article. I believe it specifies 2N3819's, though I posted it mainly as an example of a possible biasing scheme that could be implemented for a wide variety of fets with a bit of value switching. i'm sure it could be adapted to different voltages and a wide variety of fets with a some value changes.


http://www.aronnelson.com/gallery/main.php?g2_view=core.DownloadItem&g2_itemId=17356

Quote from: Dragonfly on August 21, 2008, 11:52:23 AM

Quote from: stm on August 21, 2008, 11:47:53 AM
Cool schem, Andy.  Is your circuit intended for J201's or another type of JFET?

Its straight from the Marston article. I believe it specifies 2N3819's, though I posted it mainly as an example of a possible biasing scheme that could be implemented for a wide variety of fets with a bit of value switching. i'm sure it could be adapted to different voltages and a wide variety of fets with a some value changes.

http://www.aronnelson.com/gallery/main.php?g2_view=core.DownloadItem&g2_itemId=17356

Now it makes sense, since with J201s I ended with a gate voltage around 1 volt or so, instead of nearly 2.8V.  Tonight I'll post the values I used to make a J201 bias with this method.

Cheers.

Quote from: stm on August 21, 2008, 12:14:26 PM

Quote from: Dragonfly on August 21, 2008, 11:52:23 AM

Quote from: stm on August 21, 2008, 11:47:53 AM
Cool schem, Andy.  Is your circuit intended for J201's or another type of JFET?

Its straight from the Marston article. I believe it specifies 2N3819's, though I posted it mainly as an example of a possible biasing scheme that could be implemented for a wide variety of fets with a bit of value switching. i'm sure it could be adapted to different voltages and a wide variety of fets with a some value changes.

http://www.aronnelson.com/gallery/main.php?g2_view=core.DownloadItem&g2_itemId=17356

Now it makes sense, since with J201s I ended with a gate voltage around 1 volt or so, instead of nearly 2.8V.  Tonight I'll post the values I used to make a J201 bias with this method.

Cheers.

cool - its a simple enough circuit that it may work well for some people.

Quote from: earthtonesaudio on August 19, 2008, 01:37:26 PM
I know everyone's been talking about the class-A common source configuration, but there are other ways of making gain from JFETs...

What about common gate?  If you use it as a current follower you can get voltage gain which is independent of device characteristics.  Then you just slap some source followers on the input and output, which gives you current gain while simultaneously providing good input/output impedances.  If you're willing to add the complexity of two more transistors, you can get power gain without phase inversion which is tolerant of device variations.

I have this on the breadboard right now, and it's proving to be surprisingly easy to tweak, even without coupling capacitors.  Right now it's two MOSFETs followed by one JFET, but I'm working on all-JFET and BJT/Darlington versions next. 

I don't know if anyone would be interested in exploring this more, but if so I can start another thread with some pretty pictures and stuff.

...After re-drawing this circuit in a more conventional way I discovered it's actually just a long-tailed pair or differential input stage.  Nothing new or exciting, so never mind.   :icon_redface:

Here's my take on a practical trimless JFET preamp using Siliconix AN102 mixed biasing method.
Gallery access: http://www.aronnelson.com/gallery/main.php/v/STMs-Circuit-Ideas/Trimless+JFET+Preamp-STM-rev1_0.png.html

(http://www.aronnelson.com/gallery/main.php?g2_view=core.DownloadItem&g2_itemId=28548&g2_serialNumber=2)

Schematic contains expected voltages and range of JFETs that are verified to work.
Gain is fixed at 6dB with the values as shown.  If more gain is desired, R7 can be reduced or replaced with a 10k pot.  R7=0 ohms produces a max gain of 20 dB.

Great work Sebastian!

I breadboarded the TJP this afternoon and threw in a random selection of J201s without bothering to measure them first. They all worked fine and biased up as per the schematic, subsequently measuring them showed they were all within the range of verified values. Adding a pot as Sebastian suggested makes this into a nice little booster :)

I then tried a couple of 2N5458s with VP around -2.55v and IDSS around 6mA and they worked fine as well and to my ears didn't sound significantly different than the J201s. So it looks like this circuit should work for a variety of Jfets, it would be interesting to see how far from the specified values you can go.

Quote from: slacker on August 22, 2008, 01:00:55 PM
I breadboarded the TJP this afternoon and threw in a random selection of J201s without bothering to measure them first. They all worked fine and biased up as per the schematic, subsequently measuring them showed they were all within the range of verified values. Adding a pot as Sebastian suggested makes this into a nice little booster :)

I then tried a couple of 2N5458s with VP around -2.55v and IDSS around 6mA and they worked fine as well and to my ears didn't sound significantly different than the J201s. So it looks like this circuit should work for a variety of Jfets, it would be interesting to see how far from the specified values you can go.

Great, thanks for reporting.  I'll take a look tonight to the effect of using 2N5458's in the same circuit.

No trouble, I'm not qualified to enter into the technical side of the discussion so getting the breadboard out is the least I can do.

Forget what I said earlier about it working with 2N5458s though, turns out I'd mistakenly used a 2k7 resistor in place of the 8k2 for R5. Using the correct value my 2N5458s won't work.

Quote from: slacker on August 22, 2008, 04:02:22 PM
No trouble, I'm not qualified to enter into the technical side of the discussion so getting the breadboard out is the least I can do.

I like to address engineering problems via three frontlines:

1) Math (for analysis)
2) Simulation (for design)
3) Breadboard (for testing and verification)

Each method has advantages and disadvantages (too long to detail here), but the three together allow for maximum understanding and best results IME.  I usually concentrate the most effort in 1 and 2, so any practical result is very welcome as it validates the other two!

Quote from: slacker on August 22, 2008, 04:02:22 PM
Forget what I said earlier about it working with 2N5458s though, turns out I'd mistakenly used a 2k7 resistor in place of the 8k2 for R5. Using the correct value my 2N5458s won't work.

No problem.  A quick check showed that you would need to drop the drain resistor down to 3k9 and reduce the gain resistor (in series with the 1u cap) down to 1k5 to maintain 6 dB of gain.  Of course this is just a hack on the article biasing method, as it is most likely that the gate voltage should be adjusted as well for best results.  This was with a 2N5458 with Vp=-2.3V and Idss=5.6mA (reasonably close to your device).

I use mostly methods 2 and 3 although I find the more I learn the more I use the simulator especially for trying to understand new circuits and ideas.

I should have pointed out before that using the correct resistor values the circuit worked as expected with the J201s.

Quote from: dschwartz on August 14, 2008, 10:41:18 AM
...my approach is a bit more amateur-ish, all this "Ids, Igs, Zdgs, Abc, tick tack toe" still hits me in the face, and makes me think "what the heck..i´m going for the parlor trick!!"

QUOTE OF THE YEAR!!!  :icon_lol:

Quote from: stm on August 13, 2008, 10:42:01 PM
...And it can be done. Rearranging a couple of wires around the trimpot you can have CONSTANT output impedance equal to the total trimpot value regardless of the trimpot's rotation.  The change is pretty obvious, yet I have never seen it used or mentioned before, so I decided to call it "stupidly wonderful drain biasing" or SWDB, following Mark Hammer's philosophy when naming his "stupidly wonderful tone control" or SWTC.

So, this is my newest "parlor trick": http://www.aronnelson.com/gallery/main.php/v/STMs-Circuit-Ideas/SWDB.png.html (http://www.aronnelson.com/gallery/main.php/v/STMs-Circuit-Ideas/SWDB.png.html)

After these arguments I see both biasing methods are tied, unless there is something else I am missing.

So, if I understand correctly, if you use a 100k trim pot, you get an output impedance of 100,000 ohms? Would it be possible to make the output impedance extremely low (say, 8-10 ohms) while still biasing the JFET correctly?

(http://www.aronnelson.com/gallery/main.php?g2_view=core.DownloadItem&g2_itemId=36294&g2_serialNumber=1)

Could someone explain in 10 pages or less how would I increase the output on the trimmerless jfet preamp?

Quote from: fpaul on September 03, 2008, 07:01:02 PM
Could someone explain in 10 pages or less how would I increase the output on the trimmerless jfet preamp?

in the text it mentions that, as drawn, its about 6dB gain...you can increase gain by decreasing the size of the resistor (5k6) between the 1u cap and ground...if you omit the resistor completely, you'll get about 20dBs of gain.  The layout I posted uses a pot to make the gain variable. :)

Quote from: Dragonfly on September 03, 2008, 07:41:53 PM

Quote from: fpaul on September 03, 2008, 07:01:02 PM
Could someone explain in 10 pages or less how would I increase the output on the trimmerless jfet preamp?

in the text it mentions that, as drawn, its about 6dB gain...you can increase gain by decreasing the size of the resistor (5k6) between the 1u cap and ground...if you omit the resistor completely, you'll get about 20dBs of gain.  The layout I posted uses a pot to make the gain variable. :)

But if you omit R6, there`s no DC return from source to ground  :icon_question:

go back a page and read the notes on the schematic. 

Andy was referring to R7 on the original schematic http://www.aronnelson.com/gallery/main.php/v/STMs-Circuit-Ideas/Trimless+JFET+Preamp-STM-rev1_0.png.html (http://www.aronnelson.com/gallery/main.php/v/STMs-Circuit-Ideas/Trimless+JFET+Preamp-STM-rev1_0.png.html) not R6. If you omit that and simply connect the free end of C3 to ground that gives you maximum gain.

Or what Gus just said :)

I misunderstood from Dragonflys layout the only 5.6K I could see.
I saw it physically between  the 1uF (C2 in this case) and ground.
I misunderstood omit, which in case of resistors means infinite resistance to me.

Thank you Slacker, for pointing out to me that omitting means replacing with a dead short in this case.

Quote from: snap on September 04, 2008, 09:14:09 AMI misunderstood omit, which in case of resistors means infinite resistance to me.

I'd have understood the same thing, as would be the case, say, with a pcb, where omitting the component means an open circuit. Probably not a bad idea to avoid words like "omit" in such circumstances and explicitly state whether the circuit is to be open or short.

Quote from: snap on September 04, 2008, 09:14:09 AM
I misunderstood from Dragonflys layout the only 5.6K I could see.
I saw it physically between  the 1uF (C2 in this case) and ground.
I misunderstood omit, which in case of resistors means infinite resistance to me.

Thank you Slacker, for pointing out to me that omitting means replacing with a dead short in this case.

Thats why I said ....

Quotein the text it mentions that, as drawn, its about 6dB gain...

There's no "text" on the layout, so I thought you'd know that I was referring to the text on the schematic....my bad for assuming. :)

Sorry, Andrew, my point was not so much about this particular instance, nor that you were not clear, as about using clear terminology in general--and this is one that I come across fairly often.