I whipped up a PCB for a Roland AP-7 Jet Phaser, and have finished stuffing it full of resistors and chips (thanks to the nameless good soul who posted a cleaned-up version of the original layout!). Next come the caps and FETs.
The original uses eight 2SK30-Y FETs for the 8 stages. I have that many hanging around, but not really enough to make even a feeble attempt at matching. I do have a reasonably-well matched octet of 2N5952s, though.
Can I simply sub the one for the other and use the bias adjustment to compensate for whatever differences they may have? I note that the drain-source path of each K30 is paralleled with a 100k fixed resistor in the original. My hesitance to simply just shove the 5952s in there is that I am only accustomed to seeing them in tandem with the 22k/24k parallel resistors in the Phase 90. I wasn't sure if they would provide the same sweep if subbed for the K30 in the AP-7, without any other changes.
Any thoughts?
The amount and linearity of the sweep depends on the relationship of rds to Vgs. The size of the sweep is capped on one end by rds=infinity, or as near as a JFET will get, and by rdson, which is a characteristic of the JFET type and on the specific example of JFET that type. Rds=infinity happens at Vgs=Vgsoff, and rdson happens at Vgs=0 (about).
For the typical phaser, the phasing resistor has practical limits far smaller than infinity and the 10 ohms to 500 ohms of most JFETs. As an overly-broad generality, a resistor sweep of over 100:1 doesn't change the audible result much in my experience for "typical" phasers, of which there really aren't any.
Widest sweep happens when the DC offset and AC size of the LFO waveform fed to the gate-source of the phasing JFETs exactly matches the practical limits of the rdson range and makes that fit the audible part of the sweep in the RC circuit that makes the phaser have the "best sweep" in some sense.
As you realize, there is information in those three paragraphs, but the handwaving is so extensive that there's little practical information there. :icon_biggrin:
The real bottom line is to pick a JFET which has about the same Vgsoff range as the one you're trying to hit, and then diddle with the DC offset and AC size of the LFO you feed them. The 2SK30ATM-Y datasheet says that the "Y" group has a Vgsoff of -1 to -2V.
The 5952 has Vgsoff of -1.5 to -3.5, but they don't provide the helpful curves on how to interpolate idss into a vgsoff range.
My best advice? Toss them in, and then diddle DC offset and LFO size. They're really close.
Will do.
Thanks for the help. I'll get back to you when I have something to report.
digging here
MArk, did you ever get your AP-7 off the ground?
Can you share the pcb layouts and BOMs at all please?
thanks
The board sits stuffed but unwired, amongst a very large extended family of boards in similar state, so I couldn't tell you. There ARE layouts posted around for it. One of the members here has been corresponding with me off-line, and has managed to complete his build. However, he seems to get a dead "thunk" at the bottom end of the sweep, which we haven't managed to cure yet.
Quote from: Mark Hammer on June 10, 2012, 09:44:06 AM
However, he seems to get a dead "thunk" at the bottom end of the sweep, which we haven't managed to cure yet.
I would look at the excursion of the LFO signal versus the Vgs range of the JFETs. Your description makes me think of two things.
- it is possible the positive excursion of the LFO voltage is pushing one or more gates above the bias voltage on the drain and source of the JFETs if what you hear is an audible thump
- if the "thunk" is a dead spot with no sweep and not an audible thump, then it's likely that the LFO voltage on the gates is pushing them into the highest resistance range of their rds so the sweeping is effectively not audible for part of the LFO cycle.
Hi Mark
Any chance you can PM me any project docs etc you have? I wanna make one too...
Thanks