There is a maxim from the early days of opamps: always invert, unless you just can't.  It is possible to have inverting stages with input impedances of 1M or so, even with high-ish gains. You're still going to eat the thermal noise of the input series resistor, but you're probably up for that anyway. The trick is using a three-resistor T feedback network to attenuate the feedback instead of a single series resistor.

In your case, you could probably use a 1M series input resistor and a lower-resistance (~10k's range) for lower noise in the feedback.

It's good practice to make the overall effect non-inverting, but with that many stages, surely you could find one other stage that could be changed to inverting. Might even be easier, if you're using a mixer on the output for the dry signal as many delays do. That's probably an inverting mixer followed by a second inverter, for good mixing. Drop off the last inverter.

Or if you used resistor mixing on a noninverter, now you have another opamp to do it the right way, invert->invert. And of course the final mixer can be a filter too.

Quote from: ElectricDruid on September 21, 2016, 07:04:24 AM
Ok, let's run with that for a minute. Let me slap a few values on things and tell me if I'm going wrong.
R1 & R2: Say 10K.

That's OK. They just need to be "small" for lower noise, but big enough to not pull down your power supply with too much current.

And they need to be not the same value. The bias voltage needs to be lower. You're going to want the voltage across the transistor to be about 1/3 of the standing power supply voltage; call it 3V. That leaves 1V for the emitter, 2V for the collector. You get a swing of ~2V, maybe 2.5V if you squint the R1/R2 values more closely. Then you have to make the emitter voltage be ~1V. You do this by making the base voltage be 1V plus Vbe. Vbe is about 0.7 for single bipolars, 1.2 at low currents for integrated darlingtons, and about 1.2-1.4 for discrete darlingtons. That fixes your divider network to giving a voltage for the base of about. 2.2V, not 4.5V. That's ignoring the base current drop across the series base resistor, but the higher the hfe, the lower this voltage gets - another reason to use darlingtons. Still, with hfe = 400, you're using something like 1ma for collector/emitter current, the base current will be in the range of 2.5uA, and you're losing Rbase*2.5uA to the resistive loss.

QuoteRc: Dunno. Say 100K.
Re: Dunno. 4K7? (Did I mention I'm not a transistor designer?)

That's OK, we won't tell. It's an acquired taste anyway.  I'd make Re be 1V/1ma =1K, and Rc = 2V/1ma = 2k. Hmm.  That's quite low, probably don't need that much current. OK, change to 100uA collector current. Re = 10K, Rc = 20K. This makes Ib lower, although probably not linearly lower because hfe falls off at low current (that's why differential amp multipliers work). Actually, any 1:2 ratio resistors between 1K and 10K, 2K and 20K will work OK if the following load is "high" compared to the collector resistor.

QuoteRbst: This looks like the input impedance to me. 1M.

It's not. The input impedance is the base input impedance, of hfe times Re, (between 400K and 4M for 1K and 10K Re respectively. OK, better go with the 10K-ish Re for more input impedance) in parallel with the effective value of Rbst. That's important because Rbst loses only the current caused by the difference between Vin and Ve (for AC). The difference between Vin and Ve is the one minus the voltage gain of the follwer half of the transistor. Bipolars with high gain regularly get to 98-99% gain, so call this between 0.01 and 0.02 (with darlingtons being better, but high gain singles being "ok").

That makes the effective value of Rbst be between 50 and 100 times the actual value of Rbst, and that's where the magic of bootstrapping comes in. The 4M input resistance of the base is still there, so you need Rbst-eff to be the parallel making 1M out of 4M. That's 1.3M. Then Rbst needs to be 1.3M/50 = 26K.    Actually, there are losses, so you're free to use more, like 47K, or 100K, and still get ok input impedances because of the bootstrap. This is an approximation, based on intelligent guesses about what hfe will do.

QuoteCin: Given the 1M, this only needs to be >10nF

Yep.

QuoteCbst: I don't know. What does this value get based on? Is it a HPF with Re? That'd make it about 3.3uF or so.

No, it's a HPF based on Rbst in series with the driving source and the base input resistance in parallel. If you use Rbst = 100K, something like 0.047 would be OK. But this is a place where capacitance is your friend, so why not use 1uF electro?

Forgot: the same rules apply for bootstrapping opamps, just adapted to their nature. Very helpful for things like the NE5532, which has low input impedance for an opamp.

Some tardy thoughts....

Amp design starts from a Specification. OK, we know guitar comes in, and you *say* you want gain of +2 (not proven), but what is the LOAD?

"Voltage amp" design always has a load and is thus a Power amp problem. There is no "infinite load" because capacitance sucks everywhere and there is always a frequency requirement. More often there is an audio-band load (and always capacitance). The current and collector load values must be scaled to the external load. Scaled carefully if you also need to meet an input impedance target.

Frequency response may matter. Guitar is not a tough job, we can easily exceed that, but an ADC is very liable to pull supersonic squeals down into the audio band. Guitar won't do that, but how about the clocks in your digital pedals and voltage-boosters?

Stepping back, a 3V ADC may clip at 1.5V peak. With 2X gain in front that is only 0.75V peak. I see ample evidence of 0.7V levels in some rigs. I wonder if some builders will clip the ADC. And they will blame you, not their lack of level control technique. I'd really consider leaving them plenty headroom.

Note that a single transistor amp can hardly make a peak 1/3rd of the supply. At 2X gain and hi-Z input, maybe less. +/-20% for tolerances. At 5V supply that is 1.66V peak, allow 20% and you don't get a full 1.5V swing.

Omitting 2X gain drops 6dB S/N (hiss and truncation noise). I hate that. But the better ADCs today have absurd low noise level. And guitar-chains are rarely tuned for low-low hiss. Are you sure 2X in the analog path actually gains you anything you can hear at the ear? And note that with the exception of fuzzes and power amps, ALL audio electronics runs with headroom nearer 10dB above expected peaks and 20dB above nominal (averaged) level.

I do think if hiss is any issue, any input resistor should be 10-K area, which rules out classic infinite-feedback inverters. You lose more S/N than you gain.

What is the input impedance and drive requirement of a modern 2-cent ADC? I don't know. I remember when you needed a dedicated opamp, either to force a ~~2K input, or to damp switching spikes coming out of the input. Maybe it is all so nano-sized now that you can drive with a limp noodle and get perfect response, and maybe not. A clackety input is not something they put in the chip spec headlines.

try this, seems to work on breadboard provided input is kept in the range noted. Any higher and collector runs out of headroom due to rising voltage on emitter, any lower doesn't provide enough bias.

dynamic gain = -2
I used BC547, but any generic reasonable gain transistor should work.

works on the basis that collector resistor is twice the emitter resistor, but sees the same current (neglecting the small base current) therefore must have twice the voltage developed across it.

Any data about the bias voltage providing source...??

<seems to work on breadboard provided input is kept in the range noted. Any higher and collector runs out of headroom due to rising voltage on emitter, any lower doesn't provide enough bias.>

Enough bias for what..??
(Perhaps it should stand only if you had in mind a specific signal amplitude level, but...)

Disregarding for the moment the absence of base resistor (which automatically results in saturation) I can't see any reason for not biasing Emitter much LOWER..
IMHO, lower Ve voltage leaves more space for Collector swinging..
On your scheme, 5V at base result in 4.4V at Emitter so Collector has a swinging margin of 4.6V, assuming Vce = 0..
A 1.6V at base result in 1V at Emmiter so Collector now has wider margins (8V)


BTW, the initial query was about Buffer with gain - not about X2 gain Amp with unspecified input impedance...

input impedance is transistor Hfe x emitter resistor, no need for base resistor. If a BC547C is used this will be over 400k for the values shown, which could be a little low. Maybe a 3k3 would be a better choice with corresponding increase in collector resistor. This would then give over 1.3M of input impedance, allowing reasonably high values for a resistor divider to provide bias.

I have not shown the DC bias arrangement or ac input coupling on the diagram. I would suggest 2 to 2.5 would work well from a divider . I didn't suggest an input of 5V, though the 3.5 on the diagram could be misinterpreted to be 3-5...

Quote from: Rixen on September 22, 2016, 05:35:13 PM
I have not shown the DC bias arrangement or ac input coupling on the diagram. I would suggest 2 to 2.5 would work well from a divider . I didn't suggest an input of 5V, though the 3.5 on the diagram could be misinterpreted to be 3-5...

The problem is, you can't ignore the biasing resistors. They are **critical** to the setup of the circuit, and will always be there. Simply leaving out the biasing resistor network is almost like saying "and then a miracle happens".

Quoteinput impedance is transistor Hfe x emitter resistor, no need for base resistor. If a BC547C is used this will be over 400k for the values shown, which could be a little low. Maybe a 3k3 would be a better choice with corresponding increase in collector resistor. This would then give over 1.3M of input impedance, allowing reasonably high values for a resistor divider to provide bias.

And this is one of those problems. Sure the small-signal input impedance of a BJT is hfe (note smaller case here) times the emitter resistor. But this always appears in parallel with the biasing resistors and you can't get away from that. About all you can do it to bootstrap the bias voltage so it bucks out most of the signal current lost to the resistances in the biasing.

If you don't use bootstrapping, the bias resistors get out of hand, or you lose input impedance. Somewhere around 1M, you start having real problems with thermal noise from resistors. For the 1.3M of the transistor active impedance (if you get that) to get pulled down to only 1M equivalent you need the bias network resistance to be no smaller than 4.3M, and that has to be the equivalent after the bias resistances are series/paralleled to an equivalent value. If you use a simple divider, the resistances get up to 6M-10M pretty quickly, which is why "noiseless" biasing and bootstrapping get important.

The circuit isn't complete or functional until the biasing is shown.

Quote
The circuit isn't complete or functional until the biasing is shown.

true, I should have done that.

true, the bias resistors get large, but the OP asked for a simple solution, and in my interpretation one based around a single transistor and preferably inverting.

The thermal noise of a resistor divider is equal to the noise of the parallel value of the resistors, so if it works out to 500k it is no worse than having a single 500k to ground on the input.

Quote from: Rixen on September 22, 2016, 06:52:09 PM
The thermal noise of a resistor divider is equal to the noise of the parallel value of the resistors, so if it works out to 500k it is no worse than having a single 500k to ground on the input.

There are two components - the input impedance to the transistor, about 1.3M in your example, and the parallel combination of two resistors to create the bias voltage. These two do appear in parallel.

If we want the emitter at 2V (just to pick a bias point), then for a single transistor, the base will need to be at 2.7V. If we want the input signal to "see" 1M, then the parallel combination of the two biasing resistors must be no smaller than what would parallel 1.3M to make 1M.

The conductance of 1M is 1*10E-6, the conductance of 1.3M is 1.3E-6. The conductance of the paralleled base resistors must be no greater than the difference of these, 0.3E-6, or 3.33M. We then have two resistors paralleled equalling 3.33M, and their voltage divider combination giving 2.7V from a 9V supply. With a little algebra, the lower resistor ( I call these R2...) is in the ratio to the upper one (R1) of
R2/R1 = Vb/(9-Vb) = 2.7/(9-2.7) = 0.428
Then 1/R1 +1/R2 = 1/3.3M and 1/R1 = 0.428/R2
so (1/R2)*(1+0.428) = 1/3.3M,
R2 = (1+0.428)/(1/3.3M) = 1.428*3.3M = 4.7M and R1 = R2/0.428 = 4.2M/0.428 = 11M

To check, R1||R2 = 1/(1/R1 + 1/R2) = 3.3M, and 3.3M||1/3M = ~1M ( I lost some decimal places in the rounding)

So the biasing network is 4.7M paralleled with 11M, and their noise adds as the square root of the sum of the squares of the noise voltages. The biasing resistors add several times the input noise of the transistor to the setup.

Even more importantly, the parallel combination of the two bias resistors appears in series with the base, as it must, but the base current must flow through it. With HFE (note the capitals) of 500 and Ie ~ 1ma, Ib is about 2uA. No biggie until it flows through 3.3M, in which case the voltage drop is 2E-6 times 3.3E6 = 6.6V.

Oops. You can't get there from here. You'd have to increase from 2.7V for the bias divider up to 6.6V, then refigure the bias resistors, and they'll come out to more like ~4.7M for R1 and 10M for R2, the reverse of what we figured.

To bias the transistor in this condition from a 9V supply, you almost can't use bias resistors that big with an emitter current that big. That means that going to lower collector/emitter currents is good (100uA or lower would dramatically cut the DC bias current if the transistor has enough DC HFE) and so is going to dramatically higher HFE - like a darlington.  Going to a bootstrap makes the resistor values dramatically lower, of course, as does going to noiseless biasing.

true, the circuit is not suitable for input of 1 Meg, but aiming for around 500k the values get into the lower single figures of megohms- 3.3M for R1 and 1.5M with HFE 500 (lower range for MPSA18) gives Zin ~635k, Vb = 1.73, Ib = 1uA, Ve =1.13 and Vc 6.64. With HFE 1500 (upper range for MPSA18) Zin ~853k , Vb = 2.33V, Ib = 0.47uA, Ve = 1.73V and Vc of 5.54V.

One issue, though, is the lack of headroom as when the emitter voltage (rising) gets close to the collector voltage (falling) then the show is all over..

edit - above figures assume 3.3k for emitter resistor

I think it isn't safe to assume you can protect an ADC input by planning the input gain. If it's for guitar, people will use hot pedals in front of it, or stick it in a line level send/return.

My own thoughts are that it's better to have something before the ADC that will clip or limit musically and clamp at some level just below the ADC limit. Diode feedback limiters on an op-amp comes to mind, if only a single set of diodes.

In my dreams, there's a single CMOS un-buffered inverter in a 4 pin TO-92 that will run as low as 2.5v Vdd. There is a dual 74HCU04 inverter packed in smd 6pin I think, but very fiddly of course.

Have you looked at the NPN boost ver 2/(beginner project)? as a starting point make the gain control a fixed resistor and remove the gain control cap then adjust the parts to your liking

Quote from: Rixen on September 23, 2016, 01:58:51 AM
true, the circuit is not suitable for input of 1 Meg, but aiming for around 500k the values get into the lower single figures of megohms- 3.3M for R1 and 1.5M with HFE 500 (lower range for MPSA18) gives Zin ~635k,

Maybe is useless any more, but for the record, I'm still unable to follow your calulations..

Any combination of biasing resistors & hFE X Re can't result in a Zin higher than hFE X Re itself (500 X 1K = 500k)
(any resistance placed in parallel with some other dominates the second one..)

Am I missing something on your calculations.. 
(like a "hidden" series resistance..??)

sorry, I was working on my later suggestion of 3k3 for Re... didn't make that clear.

me> what is the LOAD?

Quote from: PRR on September 23, 2016, 09:01:42 PM
me> what is the LOAD?

Yep, that's it. The executive summary is that you need a low output impedance to feed it (otherwise the sampling cap isn't fully charged by the time the ADc starts taking a reading). Obviously the extent of this problem depends on the sample rate and the required accuracy.
For "control knob" rates and accuracy (several KHz, 8-bit) I've often used a 1K resistor in front of the input. This seems to be enough to protect the input from significant overloads (+/-15V or so), presumably by limiting the current through the internal protection diodes to a level at which they *don't* die.
However, audio is a bit more demanding - both the accuracy and the sampling rate are higher (12-bit, 32KHz here).

I think anotherJim's comment about protection is useful. I haven't done anything towards hard-limiting the input (yet). Four diodes in series pairs hanging off the buffer output would limit me to about +/-1.2 which would be safe enough, so it isn't hard to do. That said, the dsPICs internal protection is pretty robust. I've run a Sequential Pro-One at full blast through the prototype with no harm done. I can't remember off the top of my head how loud (Vpp) that goes, but it's a notoriously hot output, louder than any guitar (although perhaps not all pedals).

Thanks for all the ideas. It's very thought-provoking.

Tom

> executive summary is that you need a low output impedance

"Low"?? How low is low? 10K? 1K? 50 Ohms?

I remember early audiophile ADCs needed 50 Ohms to meet audiophile tests. The switch+cap glitching would toss an opamp out of control many times a cycle. We got this with hi-current opamps on +/-15V supply then 200:56 divider so the glitching didn't go up the opamp's butt and disturb it.

This isn't a Spec yet.

Somewhere in the PIC data it ought to recommend a maximum source Z. AVR say 20k for their 10bit ADC for example, and that is, presumably if you don't exceed the recommended max sampling rate.

But I don't think Tom need worry about it. If we round the sample cap & stray to 5pF, it will still follow audio if Zsrc were 1M. Provided you are not switching an input mux to that ADC, since consecutive sample values of audio don't have big step changes, but there will be between reads of separate inputs.

As the BJT input will have some significant source Z, maybe you only need 1 set of diode clippers with a series resistor (chosen to work with Zsrc) that will divide down the signal a bit when the diodes work. Even 6db doesn't sound too abrupt to me. A pair of red LED's might just be enough.

SAR ADC clipping sounds no worse to me than op-amp clipping, but I have had latch-up if the input pin exceeds the ADC supply -  despite there being protection diodes built in to the input.

I don't know where I read it, but I recall a max Z(in) of 10k for pic ADCs. This may have been me de-rating 20k.

Surely Nyquist has demanded there be some LPF between the input buffer and the pic though?