Greetings, how's your weekend going?

I am interested in this AGC circuit and wonder if somebody could help me understand it a bit better? Just the basics. I'll figure out the rest.

Quote

PARTS LIST
R1    100kΩ
R2    470Ω
R3    10kΩ
R4    10kΩ
R5    560kΩ
R6    100kΩ
R7    10kΩ
R8    10kΩ PRESET
R9    100kΩ
C1    1µF 16V
C2    1µF 16V
C3    10µF 16V
C4    1µF 16V
C5    0.1µF (104)
C6    10µF 16V
C7    0.22µF (224)
D1    1N4148
D2    1N4148
Q1    BF245
IC1    LM741

"A portion of the op amp's output signal is rectified by the 1N4148 diodes, then filtered and fed to the gate of the FET input shunting circuit. As the output rises, more and more input shunting takes place. That is, more of the input signal is bypassed, effectively keeping the output level constant."

Think of D1, R5, and C3 as an envelope follower and that JFET as a voltage-controlled resistor.  Maybe that helps. 

Exciting, it does help! I better read up on envelope followers. I got this AGC attached after an active filter section. It outputs but does not adjust the gain.

C5 is the input cap. Goes to non inverting input of the op amp.
Ic1 op amp is doubling as an output stage and envelope detector.
The envelope is a diode charge pump type c4 to fet
The fet is attenuating the input.
In as brief as I can condense.
Just what it looks like to me.

The gain of IC1 is set by r9 r2.
R2 going to the V/2.

Quote from: Kipper4 on May 27, 2017, 08:49:58 AM
C5 is the input cap. Goes to non inverting input of the op amp.
Ic1 op amp is doubling as an output stage and envelope detector.
The envelope is a diode charge pump type c4 to fet
The fet is attenuating the input.
In as brief as I can condense.
Just what it looks like to me.

Quote from: Kipper4 on May 27, 2017, 08:54:33 AM
The gain of IC1 is set by r9 r2.
R2 going to the V/2.

Thank you Richard, that summed it up real nice and neat.