ugly face blues - GL386 clocking a 4013

[duck_arse]

it's my ugly face is the problem.

well, I've been at the 4013 being clocked by the outside world again, and lo! the glitch output strikes again. driving this time with a transistor switch. ah-hah, but this time, I found the thing. it's called "a resistor". in series with the clk input, 100k ~ 1M, and we get width in output instead of those rotten poits.

anybody with any ideas as to why?

[anotherjim]

I guess it's a noise immunity thing. Why did series resistor fix it? 4013 input has capacitance. It's a small amount of C but your resistor can be large. Your R with that C creates LP filter. Reduced noise on clock pin.
On BB, connectors add extra capacitance which won't be there when built. So less filtering with the R, but I'd bet the noise will be less then too, rendering it moot.

[duck_arse]

hah. history. I've been at clocking cmos again, started at the 4013 which would again divide only by one, until followed by the second half. then switched to the 4520, same problem. different circuit this time, a 9V Vcc phase shift osc fed to a 5V Vcc 4520, and the Q₀ output again shows pulses only wide enough to trigger the cro.

so I put in a diode/R to +/cap to ground pulse stretcher. and it works - drags the rising edge slow enough for correct output divisions and squares. the diode allows for level translation, too, and doesn't [so far] mess the pso output or shape. now I only have to work out how to make it work for falling-edge triggers.

[duck_arse]

this is the working slow-down. anyone know how to translate this for a falling-edge slowdown?

[anotherjim]

Swap R9 & C7. Reverse the diode.
But, don't the CLK only act on the rising edge? If so, what does slowing the falling edge achieve?

[duck_arse]

ah yes, well observed, but I've also been clocking the 4040, which is falling edge clocked. I'm not sure if that was exhibiting the same problem tho, will have to wait until next gets on the bb.

and, if the diode is reversed, we lose our clamping to 5V [if the circuit is not 9V supplied] ?

[anotherjim]

You would have to add safety clamping diode(s) from input to CMOS supply rail(s) separately if that's what you mean.

Look for the functional diagram in the datasheet for the counters. For some, the enable pin is actually a gate on the clock input which can be used as a clock input of opposite edge. The 4017 can be worked like that (although that Enable is called "clock inhibit"). You lose the Schmitt trigger in the proper clock input, which may be critical. Don't know if other counters have the Schmitt clock input.

[duck_arse]

sure, why not, it's only 4-ish years.

I'm at clocking a 4013 again recently, with the crash sync/blue box front end this time. and I've had the same odd pulse width problem. if I hang the cro on the f/f clk line, nice clean squarewaves in. if hung on the Q or barQ lines, nice square divides by two. if there is a resistor between Q and anything - in this case the Reset pin of a 7555, Q side of R shows fine, Reset shows ...... like a flat line, only it triggers the cro sweep. it's those tiny tiny width pulses again.

and so how can this work, the resistor eating the pulse width? still clocks the 7555, but not right. as I have only one cro channel working, to cut a long story short, I watched the Reset pin while I hung the other cro probe - connected to nothing - on the clk line, and squarewaves appear!

so it seems a cap on the clk into the 4013 is the answer; I don't know the question, tho. 39pF was same effect as 10nF, it's currently working fine with 39pF. anybody?

[duck_arse]

now with pictures.

https://i.postimg.cc/VsRtLTdJ/hollyhop-part.png

I had to mess about with the trigger signal level versus the bias voltage, and changed the placement of the isolating cap [because the 7555 Reset input is a mosfet gate and the bias was wishy-washy], and now I can't get the bad Q glitch behaviour. fixed?

the 7555 datasheet sez no inputs below -300mV or latch-ups, so D2 to clamp.


[edit :] picture now hidden.

[Ben N]

I admire persistence.
Sounds?

[anotherjim]

I'd put overshoot protection diodes to 0v and +V on the 7555 reset line so it can't get an out of range pulse when the input cap is driven. It can cause CMOS lockup otherwise. But you know that and it may not fix it anyway, but it's an easy try.

[duck_arse]

I admire persistence.
Sounds?

the only sounds are of maniacal laughter and gnashing teeth. all that persists is my inabillity to get any digital cmos to work in the vicinity of linear circuits.

so today, the make-it-work cap is 470pF, and is attached to the barQ pin. because I moved that section to the other breadboard, apparently.