Author Topic: MN300x VGG generation  (Read 2212 times)

jona

MN300x VGG generation
« on: October 27, 2015, 02:33:01 PM »
Hello folks.

I am wondering how accurate the VGG supply has to be for a MN3005 design.

thank you.

Jona

Fender3D

Re: MN300x VGG generation
« Reply #1 on: October 27, 2015, 02:43:26 PM »
You just need to be near Vdd+1V.

Watch out, Vgg will affect bias voltage requirement  AND overall gain (or loss) vs. clock.
"NOT FLAMMABLE" is not a challenge

jona

Re: MN300x VGG generation
« Reply #2 on: October 27, 2015, 02:49:43 PM »
Thanks!

Did you mean VDD -1V?

 "Vgg will affect bias voltage requirement  AND overall gain (or loss) vs. clock."

Does that mean that the closer it is to the exact value, the closer to the spec/requirements the bias/gain will be? Or should it be trimmed?

I am thinking of a design without the MN310x type parts.

thanks again Fender!

Fender3D

Re: MN300x VGG generation
« Reply #3 on: October 27, 2015, 03:44:20 PM »
Thanks!
Did you mean VDD -1V?

Vdd for 30xx is negative (-15V max) then Vdd+1 = -14V

Does that mean that the closer it is to the exact value, the closer to the spec/requirements the bias/gain will be? Or should it be trimmed?

I am thinking of a design without the MN310x type parts.

thanks again Fender!

I guess you should always trim for the best bias point...
What I meant is that with a "near optimum" fixed bias, you might as well fine tune it by varying Vgg.
"NOT FLAMMABLE" is not a challenge

jona

Re: MN300x VGG generation
« Reply #4 on: October 27, 2015, 05:09:15 PM »
ha... I missed the 'negative' part! Revisiting my initial design now, not quite sure how to deal with that. Thanks!

armdnrdy

Re: MN300x VGG generation
« Reply #5 on: October 27, 2015, 07:08:07 PM »
ha... I missed the 'negative' part! Revisiting my initial design now, not quite sure how to deal with that. Thanks!

Look to factory BBD circuits for guidance.

You feed the ground pin positive voltage and the VDD pin ground.
The BBD doesn't know the difference. The VDD pin just has to be more negative than the ground pin.
I just designed a new fuzz circuit! It almost sounds a little different than the last fifty fuzz circuits I designed! ;)

12Bass

Re: MN300x VGG generation
« Reply #6 on: October 27, 2015, 09:42:56 PM »
You just need to be near Vdd+1V.

Watch out, Vgg will affect bias voltage requirement  AND overall gain (or loss) vs. clock.

Is it reasonable to assume that the same is true for other BBDs like the SAD1024A? 

In an effort to maximize signal to noise ratio, do you know the relationship between Vgg and overall gain vs. clock noise?  In other words, does signal gain go up or down relative to the clock signal as Vgg is made closer to Vdd (i.e. Vgg = 14/15 x Vdd => Vgg = Vdd)? 

Do you have a suggestion for the optimal ratio of Vgg/Vdd, or this value something which varies from device to device?  IIRC, datasheets generally suggest Vgg = 14/15 x Vdd.  Just curious if optimal results can be obtained empirically.

Thanks!
It is far better to grasp the universe as it really is than to persist in delusion, however satisfying and reassuring. - Carl Sagan

Fender3D

Re: MN300x VGG generation
« Reply #7 on: October 28, 2015, 12:44:24 PM »
Is it reasonable to assume that the same is true for other BBDs like the SAD1024A? 

Well, SAD's datasheet says "it is recommended that Vbb be adjusted approximately one volt lower than Vdd"...

In an effort to maximize signal to noise ratio, do you know the relationship between Vgg and overall gain vs. clock noise?  In other words, does signal gain go up or down relative to the clock signal as Vgg is made closer to Vdd (i.e. Vgg = 14/15 x Vdd => Vgg = Vdd)? 

Do you have a suggestion for the optimal ratio of Vgg/Vdd, or this value something which varies from device to device?  IIRC, datasheets generally suggest Vgg = 14/15 x Vdd.  Just curious if optimal results can be obtained empirically.

Thanks!

Actually, my main concern was the signal loss when the clock was higher than ~1MHz, thus I was looking for a solution...
I tried the TCE approach, by rectifying the clock signal and feeding it to Vgg: it helped raising the gain when raising the clock, just not enough to supply the gain needed for a "steady" response... (TCE uses an OTA also...).
This approach might as well help when you have a clock wafeform not "optimal" ('cause capacitive loading or lack of buffers), but I didn't tested it for this... I used no buffer between clock and BBD.

"NOT FLAMMABLE" is not a challenge