DOD 670 Flanger Stumper

[goldstache]

DOD 670 Flanger in for service.  Can't seem to null out clipping out of the SAD512. Even tried known good IC. (Works in various other circuits)

Trimmer for input bias is operating. Seems like around 9.3vdc on the Output Side of the 4558.
Still clips a bit. Input to SAD512 is clean enough.
Clock seems to be good, and LFO that wiggles clock is performing as intended.

Just can't get it to bias clean on the wet side return. 
At center bias of 15VDC supply, (7.5VDC) There is no effect.  Only swings into operation around 9.3V on pins of 4558 wet out stage.

Couple oddities I wanted to ask about other than the above.

1- The Resistor/Cap combo out of the regeneration control wiper was switched around from the schematic.
Schemo is 22K/.047
Unit was .047/22K from wiper to pin 1 of 4558.
All pics I see online match the unit in front of me despite schematic.
I've tried both configs, no dice, and barely any difference in regeneration or bias performance.

When audio probing pins 3/4 of SAD512 it's unable to null out the clipping artifact.

2- The Inputs of the wet output 4558 stage shows a 33K feed from SAD512 to + input via a 62K resistor. Here's the misprint (gotta be, kills flange).  Shows that same 33K feeding the inverting input as well.
That's gotta be wrong. Not connected that way on this PCB. Don't really see that sorta output stage config, so it's likely a misprint.

All voltages seem good and I do have sweet sweet flange, just with a dose of crackle from the delay chip.
SAD512 Voltages.
Power- 15V
Pin 6    5.3V
Pins 3/4  9.3V ( only voltage it biases at +/- 200mv)

Schemo attached with some previous annotations. Possibly for unit with different delay line IC, maybe?

[Govmnt_Lacky]

Perhaps a bad 571 Compander??

[Mark Hammer]

Is it clean with NO regeneration?  If you look at the Boss BF-2, you'll see that the op-amp stage, which combines feedback with incoming signal to feed to the BBD, has a "soft clipping" diode pair to limit how hot a signal the BBD receives when the regen is maxed.  Here there is no such protection.  Granted, it uses a compander to keep clock noise low, but the feedback path lies between the output and input of the BBD.

[ElectricDruid]

I'm not sure about the bias problem, but I can answer the other questions.

(1) is not an issue since it's a series connection, so it doesn't matter which way around they are. Yeah, the schematic is probably wrong.

(2) The schematic *is* wrong. I've got a copy I found somewhere named "DOD flanger 670 (corrected)" and that's one of the differences from the one you've attached.

Here's the other one for comparison:

[goldstache]

Thanks for suggestions. Compander chip has been explored and swapped for known working. No dice there.

Regarding input clipping on SAD, seems pretty clean from 570(1) compander to input of SAD. Distortion is present only on output of chip.  After reading the Application Note for the SAD, I'm wondering if VBB supply, instead of referencing the power rail, perhaps a divided supply a volt or so lower for VBB may help???
I lightweight understand that the +/- output pins are summed to cancel clock.  So is it safe to assume that the pins being strapped (Pins 2/3) may contribute to me not being able to null clock for biased play.

In summary:
- Vbb pin5 referenced lower than supply rail?
-Possible trim pot for Pins3/4 for balancing odd/even output?

Also, I did already put a known working SAD chip in that position and got the same artifact.  So I believe it stems from the surrounding circuit components. Unit has been serviced and all the bad/sketchy stuff is already out of there.

The other question is about the clock and it's performance. Can't seem to see any voltage charts for the CD4001, but I already socketed and used a new one to check.  In the data sheets for the SAD chip it sorta states that clock voltage should lie between 5v and supply. Out of the last stage of the CD4001 I'm only seeing around 500mv clock pulses.  Not near 5V?
The 2N4124 tests remedially good (diode check). But perhaps thats an issue?? Just not really certain what voltages I'm supposed to see there.

I would think that the clock is operational, as I have flange and clock is modulating. But not sure if that control voltage needs to be larger to bias in.

[goldstache]

Druid, good sir.
Thanks.
The only discrepancy I'm seeing from the actual unit to the schemo you provided, is the Vref divider for the 4558 has a 470K reference resistor instead of the 100K in schemo. Not much of an issue I'd figure, even with all the shared reference to the chips.

Ohh yeah, and the inverting pin feed setup of the wet return 4558 stage. Your schemo is correct there!

Cool, thanks.

[ElectricDruid]

The other question is about the clock and it's performance. Can't seem to see any voltage charts for the CD4001, but I already socketed and used a new one to check.  In the data sheets for the SAD chip it sorta states that clock voltage should lie between 5v and supply. Out of the last stage of the CD4001 I'm only seeing around 500mv clock pulses.  Not near 5V?
The 2N4124 tests remedially good (diode check). But perhaps thats an issue?? Just not really certain what voltages I'm supposed to see there.

I would think that the clock is operational, as I have flange and clock is modulating. But not sure if that control voltage needs to be larger to bias in.

This is old-school 4000-series CMOS running on 15V, so you should be seeing 0-15V signals, not 0-5V. If it is actually flanging, then it's clearly doing something, but I'm a bit surprised you can't see decent clock signals somewhere. Can you check those various 4001 NOR gate outputs on an oscilloscope?

Add another schematic error, I guess - there's no power supply connections shown for the 4001. It's "assumed". You can get away with that when it's drawn by hand. A CAD package would have a dicky fit.

[goldstache]

To be honest I did just scope the 4001 and got a look at the clock pulses. They looked ok, lol. But the actual clock voltage to pin 1 of SAD never gets above 500mv.  My thought was that the BJT in that section just provides the Freq range. I'll post some voltages here once collected. And get cycle and freq measurements while I'm in there.

[goldstache]

Here's some findings:


Voltages:
LM324
1- .6V - 8V
2- .6V - 1V
3- .6V - 1V
4- 15V
5- 5V - 9.1V (abrupt shifting)
6- 5V - 9.1V (smooth cycling)
7- 13.7V
8- 6.3V - 8V
9- 137mv
10- 120mv
11- GND
12- 1.3V
13- 1.3V
14- 1.3V

4001 IC:

1- 14.91V
2- 14.91V
3- 145mv
4- 82mv
5- 14.91V
6- 14.91V
7- GND
8- 193mv
9- 193mv
10- 14.9V
11- 196mv
12- 9.58V
13- 9.58V
14- 15V

Then here's some clock info: read from pin 1 of SAD chip. Never dips below 90Khz. And with Manual ("depth") maxed (full CCW) around 400khz.  1-6us period when set semi slow speed. The clock is definitely getting tickled by the LFO (Speed) and width is visually present, and of course measurements change with changing the the "manual" depth control. Which looks like just sets delay amount.

I stuck the scope on the tied together output pins of the SAD chip, and playing with that network headed out to the 4558, depending on network and bias the 1K input sig looks pretty good headed to the SAD chip.
100mvac input to compander yields 200mv output to SAD chip.  When I lower the input to delay line, it cleans up a bit, and output doesn't look clipped up top.

Lower gain in 571 input stage maybe?

Here's the schemo Druid was kind enough to include, with Pins added to schemo for help keeping stuff straight.
Many thanks.

[goldstache]

Think I got it sorted oh vey. 

The gain from the 571 chip was just too much for the input headroom of the SAD chip.
The split 33K's on the input comp chip, had a 4.7uF cap there that tested good, but once I checked capacitance, bingo. 17uF

Clipped (-) terminal real quick and clean operation restored.  So I'll play with cap values there and see what lets humbuckers womp on em without overdriving the SAD. 

Thanks for the insight and well....commiseration.