Measurement of Vp and Idss

[mwelch55]

I was reading the Fetzer Valve page on runoffgroove trying to better understand the meaning of "Gain".  There is an example below of the J201 that says it has a gain of 4.8 times or 13.6 dB and an example of the MFP102 that says it has a gain of 1 times or 0 dB.  If a transistor has a gain of 1 times or 0 dB, does that mean there is no signal amplification?

Out of ten (10) J201
average Vp: -0.83V (spanning from -0.57 to -0.97)
average Idss: 0.64mA (spanning 0.30mA to 0.83mA)
average Rs: 1076 ohms
average Rd: 10321 ohms
average Gain: 4.8 times or 13.6 dB

Out of twenty-four (24) MPF102
average Vp: -2.34V (spanning from -1.76 to -3.11)
average Idss: 5.65mA (spanning 3.91mA to 7.15mA)
average Rs: 344 ohms
average Rd: 688 ohms
average Gain: 1 times or 0 dB

[PRR]

> I was reading the Fetzer Valve page on runoffgroove

Link?

[GibsonGM]

http://www.runoffgroove.com/fetzervalve.html

[MaxPower]

If I recall they're talking about biasing the jfet where it most closely sounds like a tube (harmonic content). So depending on vgs( off) and Idss, the circuit may have unity gain, or less.

[ElectricDruid]

In section 7 Stage Gain they say:

The gain of the first 12AX7 stage in the Fender amp is near 35 dB or 50 times.

The gain of the proposed JFET stage is calculated by:

Av = 0.5 * Rd / Rs

Replacing the optimal values for Rd and Rs gain can be also expressed as:

Av = 0.54 * (Vcc/|Vp| - 2)

Some remarks on the gain formulae are:

Rd must be greater than twice Rs or the gain will be less than unity.
Vcc must be approximately greater than 4*|Vp| or the gain will be less than unity.
Gain depends on Vcc and Vp only, and is independent of Idss.
Gain increases as Vcc is increased or |Vp| is decreased.

Example: Consider a MPF102 whose Vp=-3V. If a 9V supply is used, gain will be 0.54 times or -5 dB, which is less than unity! If the supply voltage is doubled to 18V, the resulting gain will rise to 2.2 times or 7 dB!

Example: A J201 with Vp=-0.6V fed by 9V will have a gain of 7 times or almost 17 dB. (However, as we already know this stage will clip as soon as the input voltage exceeds the +/- 0.6V range.)

However, I can't make the example calculations add up. Take the first MPF102 example:

Av = 0.54 * (Vcc/|Vp| - 2) = 0.54 * (9/3-2) = 0.54 * 9/1 = 0.54*9 = 4.86.

They claim x0.54, which would need the bit in brackets to be one. This doesn't make any sense. What am I missing?

[diffeq]

In section 7 Stage Gain they say:

The gain of the first 12AX7 stage in the Fender amp is near 35 dB or 50 times.

The gain of the proposed JFET stage is calculated by:

Av = 0.5 * Rd / Rs

Replacing the optimal values for Rd and Rs gain can be also expressed as:

Av = 0.54 * (Vcc/|Vp| - 2)

Some remarks on the gain formulae are:

Rd must be greater than twice Rs or the gain will be less than unity.
Vcc must be approximately greater than 4*|Vp| or the gain will be less than unity.
Gain depends on Vcc and Vp only, and is independent of Idss.
Gain increases as Vcc is increased or |Vp| is decreased.

Example: Consider a MPF102 whose Vp=-3V. If a 9V supply is used, gain will be 0.54 times or -5 dB, which is less than unity! If the supply voltage is doubled to 18V, the resulting gain will rise to 2.2 times or 7 dB!

Example: A J201 with Vp=-0.6V fed by 9V will have a gain of 7 times or almost 17 dB. (However, as we already know this stage will clip as soon as the input voltage exceeds the +/- 0.6V range.)

However, I can't make the example calculations add up. Take the first MPF102 example:

Av = 0.54 * (Vcc/|Vp| - 2) = 0.54 * (9/3-2) = 0.54 * 9/1 = 0.54*9 = 4.86.

They claim x0.54, which would need the bit in brackets to be one. This doesn't make any sense. What am I missing?

Division and subtraction order, which should be more clearly represented with another pair of brackets:
0.54 * ((9 / 3) - 2) = 0.54 * (3 - 2) = 0.54 * 1 = 0.54 [9V variant]
0.54 * ((18 / 3) - 2) = 0.54 * (6 - 2) = 0.54 * 4 = 2.16 [18V variant]

[ElectricDruid]

Ah, ok, thanks very much. That helps a lot.

That's me being too literal-minded and reading it like it was a computer program...sorry!

[PRR]

Yes, *this* scheme assumes biasing at a large fraction of Idss and just 9V supply. This is a poor plan for gain.

Note: "Vcc must be approximately greater than 4*|Vp| or the gain will be less than unity."

If part is 3Vp then Vcc (supply) must be greater than 4*3V = 12V or the gain will be less than unity.

With Vcc at 24V, the same part gives gain near 4.

We can do very much better than this by deviating from the "Fetzer" plan. However peak guitar signals are a not-small fraction of our usual 9V supply, so we can't get a lot of gain, or maximum level. Take a device with Vp=0.5V, non-Fetzer design, we can probably get gain of 15, but maximum input may be 0.2V peak, and guitars deliver more than this with hard strumming.(*)

(*)They say "The first valve stage of a Fender amp can withstand input voltages up to +/- 2.5V without noticeable clipping." I believe this should be 1.5V-2V peak, though "noticeable" is a vague spec. I also assume that we "need" this much input headroom, because Fender also gives you a 2:1 input pad for extra-hot sources, and because plans with lower input overload (one Traynor I had) have not been popular.

[PRR]

Forget "gain". There's better ways to get gain, predictable, cheap. Opamps. BJTs for the masochists.

The Fetzer plan promises "nice distortion". Something you don't get from simple opamps or BJTs.

I simmed their suggestion. I used an imaginary JFET with Vp=3V and Idss=12mA. I took their calculator's suggestions as given. Because this is a high Vp FET on a low supply voltage, indeed the gain is small. Just looking at their suggested resistors, 236/207 promises gain a hair higher than unity. With any real FET there is an additional rs, the FET's internal source impedance. The idea of the Fetzer is to make rs similar to Rs to cut the excess nonlinearity of the FET. This leads to gain of about half. Calculator predicts 0.6 and sim gives 0.56. 2.5V peak input clips slightly. 2V peak input gives 1.12V peak output with 6.66%THD, both even and odd, falling-off as a simple device should.


Small differences between calculator and sim may be due to different model simplifications in Fetzer and SPICE; also I took the Vp and Idss numbers carelessly (knowing that real devices will always be different). I don't see anything invalid.

We can easily get "more gain" from this high-Vp device by running at lower current. But does that screw-up the distortion product?

[PRR]

Some quick trials suggest that lowering the current (to raise gain) makes the R a too-large part of the total source impedance. Distortion, especially even-order, goes down much faster than gain goes up.

*GIVEN* a 9V supply, the optimum seems to be to pick a Vp about 10% higher than your peak input voltage. Using my rule of thumb (1V peak), use Vp=1.1V (1.0V-1.2V). Pick an Idss to give a reasonable Rd, probably 0.5mA-2.0mA. Use the ROG calculator to get values. Gain will be about 3.4; this is of course "all" the gain you can use for a 1Vpeak input and about 3.4Vpeak output (6.4Vp-p under 9V rail and a couple Volts for the FET).

[Rob Strand]

We can easily get "more gain" from this high-Vp device by running at lower current. But does that screw-up the distortion product?

The motivation behind the Fetzer was to approximate a tube.  It basically adds the source resistor to linearize the square-law of the JFET so the square law becomes more like a 3/2 law.    It can only ever be an approximation.  Like most approximations there's a region where there are different approximations with none being exact.

There are two things fixed in the Fetzer design,
1)  The bias point always chooses VGS = 0.35 * VP.
      The sets a particular trajectory on the JFET square law.
2) The drain resistor is chosen so,

          VD = 0.6*Vcc + 0.7*|Vp|

However: There's actually some bugs in the calculations in that the values displayed by the Fetzer Calculator are *not self consistent*.  That's why a spice sim never matches up.  The calculated drain resistor actually works out to give,

           VD  = 0.62Vcc + 0.76 |VP|

The whole starting point for  Fetzer design is to set VGS = 0.35 * VP.
That immediately determines the quiescent drain current and the source resistor,

      ID = 0.4225 IDSS
      Rs = 0.828 VP/IDSS

One thing not so obvious is when VGS swings to the point where VGS= 0,
the drain current approaches ID = IDSS however the choice of RD
never lets the VDS voltage across the JFET get to zero it always
current limits at ID = IDSS.   At that point it's possible to show,

     VD = 1.8*|VP| + 0.1Vcc
     VS = 0.828 |VP|

So it's clear VS is always less than VD.

The Fetzer calculations always end-up with a reasonable bias point both on the gate and the drain.
One way to get more gain is to simply bypass source resistor with a cap or a cap in series with
a resistor.    With the source resistor bypassed it's possible to choose a slightly larger Rd to squeeze
a bit more gain and still not let VDS=0.   However, all that breaks the approximation to the 3/2 law. 
Something has to give.  The other way to get more gain is to increase the supply voltage; technically
that won't break anything.

[lcv]

BTW one thing that I never understood, on the fetzer de lux section,  about the Rs bypass cap calculation:

The value of this capacitor depends on Rs and the desired knee frequency fn, and can be calculated as:
Cp = 1 / (2*pi*Rs*fn)

I'would expect  that the cap value  should be calculated against Rs//rs not Rs alone.
May be I am missing something.

[PRR]

It's a shelf. The lower corner is at Rs. The upper corner is at Rs||rs.

[lcv]

Oh yes! thank you for the clarification.
Moreover , I think that   if  rs=Rs,   the zero and the pole  frequencies coincide, so the result (for a given target frequency) is the same anyway.
Regards
Luca

[PRR]

> if  rs=Rs,   the zero and the pole  frequencies coincide

No. Does not make sense.

If the two resistors are VERY different, the two poles can be computed separately.

When rs=Rs we have a 6dB shelf. The two poles affect each other. The -3dB point shifts. For a 6dB shelf, -3dB happens at the geometric mean of the two poles.

This sim is adjusted to 6dB shelf, showing that re=Re. We compute 1uFd against 800r as 200Hz, and 1uFd against 800r||800r (400r) as 200Hz. What we get is the 200Hz pole is "up 3dB" at 280Hz, and the 400Hz pole is "down 3dB" at 280Hz.

[lcv]

PRR
Thank you, my mistake!

Luca

[mwelch55]

Thanks for pointing out that increasing Vcc or making Rd greater than twice the Rs value will make the Av (V/V) value greater than 1 for the PN4392.  I hadn't noticed that.

Is there a case where you would want the gain of an FET to be less than unity gain?

[PRR]

> Is there a case where you would want the gain of an FET to be less than unity gain?

Considering that a 19 cent TL072 gives *TWO* lumps of predictable gain, is there any real reason to also be asking for gain from unpredictable JFETs?

Use the JFETs for *distortion*. Something you can't get, sweetly, from chips. If the gain of the JFET comes out to be "half", then shove 2V in, get curved 1V out. No real problem bringing 20mV guitar up to 2V, or adjusting that 1V out up/down to suit your next stage.

Yes, this does blow a hole in the idea of "JFET replacements for 12AX7 amplifiers", where all bottles in a Bassman etc are "simply" filled with JFETs making all the gain. Such things can be nice musical tools, for sure. But unless run on much higher voltage, the "Fetzer" plan has to be tinkered to get the gain.

[Rob Strand]

FYI:  Here's an article which gives a way to find the value of the source resistor to give a 3/2 law.

http://www.diale.org/triode.html

So you choose,

     Rs  =  k * |VP| / IDSS

Fetzer choses k =  0.828
and the recommendation in the link is k=0.8409.

The thing to note the graph of "n vs z" about halfway down the page.

You want to n = 3/2 but there is no single value of k which gives n = 3/2
for all input voltages 'z'.   The author chooses z = 1/2, in the middle, and
that gives k=0.841.   

Who is to say what value of z is gives the best tone?
If you choose z a little bit less, say z=0.38 we need k = 1 (approx).
If we choose z at a high input, say z = 0.9, we need k = 0.6 (approx).

You could argue to choose smaller k values for later stages since they see higher signals, and that will allow higher gains.  You could also argue for larger k values for early stages.  For small signals you could argue the device behaves fairly linearly anyway so maybe it's over doing it trying to match the 3/2 curve at the expense of gain (if that's what you need).

[Eb7+9]

The motivation behind the Fetzer was to approximate a tube.  It basically adds the source resistor to linearize the square-law of the JFET so the square law becomes more like a 3/2 law.

Rob,

the so-called 3/2 power function is a very poor approximation to triode output curves

see here for a popular source:

http://leachlegacy.ece.gatech.edu/papers/tubeamp/tubeamp.pdf

super impose the 12ax7 Leach graph against tube data
and easily conclude that a 3/2 power expression
is, let's be frank, not very accurate beyond its basic
qualitative function ...

not discounting the validity or usefulness of
Leach's article ...
rather, blind obedience to this 3/2 factor thing

notice otoh the input circuit response for Triodes is never published
(that's where modelling/simulation comes in handy)

—-

Next, the quadratic nature of jFETs

we all know there are two quadratic functions used to describe jFET Drain current functions

There's the one as a function of Vgs, the input circuit set

and then, there's  the one as function of Vds but this applies only in the narrow ohmic region, outside of the main useful region

Obviously the part that is fully quadratic (not purely either) across the whole span of operation is only the input circuit response

—-

So, my point:

comparing non 3/2 power output response of tube (triode)
against sorta quadratic input response of jFET

... like comparing bananas to hotdogs

the same oversight appears in Temuk's ieee paper

—-

IMO, a more proper basis of comparisons between "tubes" and jFETs can/should be established as follows:

as far as large signal behaviour is concerned a somewhat similar concavity in the input circuit response of jFETs and both types of tubes (Triodes and Pentodes) can be said to exist - tho with one important difference: in the jFET case the turn-off voltage is fixed whereas w tubes
this point moves w anode voltage

as far as small-signal cases goes the output impedance profile is somewhat comparable, at least qualitatively, between jFETs and Pentodes ... whereas w Triodes the output impedance is much lower ...

tho to a dweller living in load-line land the monotonicity is still there and things look similar other than a difference in lateral slope - which then implies a scaling of loads

from these observations I submit that the main basis for comparing "tubes" to jFETs lies in the similarity that exists between input circuit responses ... and not much else

—-

instead of getting hung up on emulating device characteristics have a look here for a DC-coupled solution to approximating the classic triode-circuit response:

http://www.lynx.net/~jc/transferCurvature-TubeSimulation.htmlTo