Switchable onboard buffer for otherwise passive bass

[PRR]

> the fact that is a JFET gate?

Which conducts HARD ("infinite") if taken past +0.7V or -35V. Both of which can happen on a stage. Look-up JFET data, and consider what crap they may survive with zero or 10k in series.

[Fancy Lime]

> the fact that is a JFET gate?

Which conducts HARD ("infinite") if taken past +0.7V or -35V. Both of which can happen on a stage. Look-up JFET data, and consider what crap they may survive with zero or 10k in series.

Ah, I see. Thanks!



BTW, here is the corrected layout:



Andy

[merlinb]

So are you gonna reduce R1?

[Fancy Lime]

So are you gonna reduce R1?

Well... I don't know, really. I mean, unless I know what voltage and total charge I want to protect the input against, R1 is pretty much a stab in the dark, is it not? The 2SK117 can tolerate 10mA at the gate, so with a 10k resistor I can protect it from up to 100V. Not a lot for ESD. Then again, there is also C1, which will eat some charge before we even need to start worrying about voltage. And ESD pulses usually have relatively small charges. How small? No idea. I feel like the R1-C1 combo should somehow take care of the the charge variable but I am way to tired right now to figure out how. But the smallest voltage deviation from the bias point at the gate that we need to avoid is 4.5V + 0.7V on the plus side. To get 5.2V across the 100nF cap, we need 520nC of charge. Is that realistic for the type of ESD we want to protect against? I don't have the slightest clue.

TL;DR: I stuck with 10k for R1 because that is what Boss do in all(?) their JFET input buffered pedals. Is that a great reason? No, but it is the only one I have at this point. Better reasons to change it will be greatly appreciated. Basically, I would need to know what discharged (V and Q) I am up against. I won't be sticking parts of the instrument in a mains socket, so maybe 100V protection against large-charge sources is overkill. Maybe I'll get hit by lightning while playing and should install a kilofarad supercapacitor for C1. But those can only take a few volts at the moment, so maybe lightning protection will have to wait until capacitor technology catches up.

Andy

[merlinb]

I'd use 1k at most, otherwise all that talk about wanting low noise is moot. If you need ESD protection, use a small series inductor or break R1 into two 470R resistors in series, with diodes to each power rail from the junction of the two resistors.

[amptramp]

ESD protection often takes the form of a pair of reverse-biased diodes from the input to ground and the power rails.  If the input goes below ground or above the power supply, the diodes conduct and short out the ESD, limiting it to just beyond the rails.  You may still need a series resistor to avoid blowing the diodes.

[Fancy Lime]

I know the "reverse diodes to both rails" protection scheme from MOSFETS but have never seen in on JFETs and started to wonder why. I tried to find useful info on ESD protection for JFETs and did not find much very useful info. So, reluctantly, I had to use my own brain:

A positive ESD pulse on the gate means that the G-S junction starts to conduct. So voltage in itself is not a problem here but may become one if the current into the gate exceeds 10mA (for the 2SK117). So uncle Ohm says that if I place a 1k resistor right in front of the gate, anything below +10V over forward breakdown is OK. Forward breakdown should occur at Vgs=+0.7V, which happens when the gate is a positive suppl plus 0.7V. 

In the other direction, I need to worry about G-D breakdown, which is at a minimum of -50V for the 2SK117.

So for a JFET like this, I think I should be in the clear with a single 9V1 Zener diode and a little rearranging of the components like so:
Input > C1 > 9V1 Zener reverse to ground > R1 (1k) > gate
This means that the gate can only swing from 0.7V below to 9.1V above ground (which is slightly outside the maximum range intended for normal usage)and will never see it's maximum gate current exceeded.

The only thing I was worried about is that the leakage of the diode may upset the gate bias. So I put it in and checked and got some very unexpected readings.
In the circuit as it is in the last schematic I get:
Power supply: 9.21V
Bias network point (junction R2, R3, R4): 4.29V (so far so good)
Gate: 2.95V
Source 4.70V
So I'm thinking R2 is too big at 4M7 and the gate current is pulling the bias low. But how, when the drain sits at 9V and the source at 4.7V? How can anything in the JFET drag the gate lower than any of the other terminals are? Anyway, I tried to stick in a reverse 9V1 Zener straight from gate to ground to see if that would pull the gate too low. But it did the opposite, it pulled the gate up to 3.26V. What the FET? If the only thing I changed was to add another connection to ground, how can the point that is now "more" connected to ground go further away from ground? I checked all connections and readings five times to make sure I'm not just being stupid. Any idea what's up with that?

I changed R2 to 2M2 to see if I get a more reasonable bias voltage at the gate and indeed it went up to 3.55V. Now sticking in that Zener does not change the voltage at the gate anymore. The source voltage also stays nailed to 4.70V.

Here I was, naively thinking I finally had a bit of a handle on JFETs...
Andy

[merlinb]

How can anything in the JFET drag the gate lower than any of the other terminals are?

Your multimeter is pulling the gate voltage down when you try to measure it.

[Fancy Lime]

How can anything in the JFET drag the gate lower than any of the other terminals are?

Your multimeter is pulling the gate voltage down when you try to measure it.

Ah yes, that checks out. So I was being stupid after all. Disregarded the old rule to never trust measuring equipment blindly. I checked the apparent voltage between the gate and the supply rail (with the 4M7 for R2 back in) and got -3.58V. So yes, my DMM is pulling the gate around.

What I still don't understand, is what that diode does to the voltage reading. With the diode in (9V1 Zener reverse to ground straight from the gate), the apparent voltage at the gate is pulled up from 2.95V to 3.26V (compared to without the diode) when measuring with reference to ground. When measuring from the power rail, on the other hand, the apparent voltage goes down from -3.58V to -3.62V when inserting the diode. I don't understand that at all.

I tried to figure out the "equivalent resistance" of the reverse biased zener at 4.5V, to see if it would noticeably mess with my bias for real or if that is again some artifact. I put two 9V1 zeners in series between the rails (reverse biased of course) and measured the center point vs ground. That read 2.25V, which we have established is bull$#!+ but we can use it anyway. I checked the same point against the supply rail and lo and behold, -2.25V. The rails are, just for a sanity check, 9.21V apart. So I swapped the upper one of the diodes out for resistors to get the same 2.25V against ground reading, figuring that that would give me the "equivalent resistance". I went up to 32M, where I got 2.9V and had no more large resistors lying around on my bench. So that tells me, unless I'm being stupid again, the equivalent resistance of the 9V1 zener, reverse biased with 4.6V, is >32M. So It should not mess with the bias too much. But possibly enough to justify going down to 3.3M or 2.2M on R2. Should not make an audible difference anyway. I'll test it.

Thanks and cheers,
Andy

[merlinb]

But possibly enough to justify going down to 3.3M or 2.2M on R2. Should not make an audible difference anyway. I'll test it.

Stop measuring the gate voltage, measure the source voltage. Does it change when you add the Zener?

[Fancy Lime]

But possibly enough to justify going down to 3.3M or 2.2M on R2. Should not make an audible difference anyway. I'll test it.

Stop measuring the gate voltage, measure the source voltage. Does it change when you add the Zener?

Good point. Source voltage changes reproducibly but very slightly from 4.70V without to 4.67V with the diode. So I'll put that down as a non-issue, shall I?

Thanks for all the mental hand holding,
Andy

[antonis]

So I'll put that down as a non-issue, shall I?

We should be grateful, Andy..