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## Help with the simulation of Phase 90 on LTSpice!!! JFET's giving 0.3 Volt sweep

Started by savethewhales, September 05, 2020, 11:17:12 PM

#### Rob Strand

QuoteSo that's definitely a source of a problem.  I can't see why on your sim.  Maybe probe the DC voltages on the power pins of U7 or check the connections on the schematic.    See if you can work out why U7 isn't swing to the correct voltage.

Do you actually have a -Vcc power source?  maybe U7 is running from nothing on the negative rail?
Send:     . .- .-. - .... / - --- / --. --- .-. -
According to the water analogy of electricity, transistor leakage is caused by holes.

#### savethewhales

Quote
What do U11 U12 do ?

If R38 e R39 is made a 10k pot, why does it need U10?

C11 and C12 different values opposite directions?

R32??

It does not have to be this complicated.

U11 and U12 separate the astable output from the Vfullrange part and the Vfullrange from the depth, respectively. Actually I've done this because when I changed one of the parts, the output would behave as if I was chaning the other one too, which was something I didn't want. Same thing with U12 (separating).

C11 and C12 serve as a solution for me not having a 10uF polarised capacitor. When in reverse series, the equivalent value is 1/(1/C11+1/C12). In this case I get a 9.09 uF polarised capacitor.

R31=Pad for the speed of the triangle, without it I was getting too fast of an LFO and R32 is a 470k pot that defines the speed of the triangular wave.

#### savethewhales

#142
Quote from: Rob Strand on October 26, 2020, 05:33:28 AM
I'm assuming you are only interested in the oscillator around U7 and U8.

Yes!

Quote
Also the sims are the signals at those IC's.  Yes?

Yes!

Quote
So I started with these equations...

...The opamp VOH and VOL are the output levels at the point marked SQUARE, the output of U7.
ok!

Quote
Your equations use +/-Vcc but in reality VOH is about +Vcc-1.5 and VOL is -Vcc + 1.5V, as the opamp doesn't swing fully to the rails.

So here's where I get confused.   On your sim U7 is powered from +/- Vcc  so you would expect U7 to swing +/-Vcc (or the more accurate levels I just quoted).   However your U7 is swinging 1.5V to 7.5V.   It looks like U7 is powered from 0V and Vcc.
It is right then everything you said. Power is +9V to 0V, sorry for not bringing this here before.

Quote
Also I couldn't see what voltage you used for Vref on the schematic.

Vref is 4.8 Volt exactly (coming from the 5.1V Zener)

QuoteDo you actually have a -Vcc power source?  maybe U7 is running from nothing on the negative rail?
This is how my circuit is operating (I know it's strange but helps me understanding the working of the LFO itself)

#### Rob Strand

#143
OK, so when I plug in the values I get a good match with your spice sim.
Notice I'm using 1.5V and 7.5V for the opamp swing.

Thresholds:
VLO = (1 + 47k/270k)*Vref - VOH * 47k/270k
VHI = (1 + 47k/270k)*Vref  - VOL * 47k/270k

Opamp Swing
VOH    7.5
VOL    1.5

Vref    4.8

Calculated
VLO    4.33
VHI     5.37

Value by eye from spice output
VLO    4.4
VHI     5.35

The calculations and the spice output agree to better than 0.1V

So perhaps the problem was you used -Vcc as -9V instead of 0V?
Send:     . .- .-. - .... / - --- / --. --- .-. -
According to the water analogy of electricity, transistor leakage is caused by holes.

#### savethewhales

Quote from: Rob Strand on October 26, 2020, 06:28:57 AM
Thresholds:
VLO = (1 + 47k/270k)*Vref - VOH * 47k/270k
VHI = (1 + 47k/270k)*Vref  - VOL * 47k/270k

Opamp Swing
VOH    7.5
VOL    1.5

Vref    4.8

Calculated
VLO    4.33
VHI     5.37

Value by eye from spice output
VLO    4.4
VHI     5.35

The calculations and the spice output agree to better than 0.1V

yesyesyesyes that's indeed right. Thank you so much. I guess I was confusing the equations (but not confusing -vcc actually)

#### savethewhales

Is it right to assume that the inverting and non-inverting pins in the schmitt-trigger have the same voltage Vref?

Actually I already understood that yes, they do, because I did the math to get to the equation Rob posted here, but I wanted to know if there's anything else to take into account around this matter.

Thanks

#### savethewhales

Well I actually am trying to get to Rob's equation by node analysis and I don't seem to be getting it right..

I am considering now the V+ point differently from the Vref point, and the way that I am dealing with the Vin being leftover in the equation is by subtracting the VLT from the VUT but in that way I can't seem to discover what Vin actually means.. Could I substitute it for the value of Vref? No, right?

#### Rob Strand

QuoteIs it right to assume that the inverting and non-inverting pins in the schmitt-trigger have the same voltage Vref?
That's the main idea.

Quote
Actually I already understood that yes, they do, because I did the math to get to the equation Rob posted here, but I wanted to know if there's anything else to take into account around this matter.

For more accurate results you can take into account the fact the opamp output doesn't swing 0V to VCC but swings approximately VOL=0V+1.5V = 1.5V to VOH = VCC-1.5V = 7.5V.

That's a finer point which makes things more confusing.   It also makes the equations a little messier.

Quote
Well I actually am trying to get to Rob's equation by node analysis and I don't seem to be getting it right..

I am considering now the V+ point differently from the Vref point, and the way that I am dealing with the Vin being leftover in the equation is by subtracting the VLT from the VUT but in that way I can't seem to discover what Vin actually means.. Could I substitute it for the value of Vref? No, right?

Well I could have made a mistake but I was fairly convinced the equations were OK since it matches the sim.

It can be confusing analysing Schmitt trigger because it has a two states.    You are currently in one state and you want to find what input voltage changes the state.   There are two states and two such voltages.  The change of state occurs when the opamp input voltages are equal.

The best way to start is to "pick" a stable state to start in.  So if you think of the input as being low opamp +input will be below -input and the opamp output will be low.     The opamp output being low is consistent with opamp +input still being low, so it is stable state.

You want to opamp output to change from the stable low-state to high.  To do that the opamp + input must rise towards Vref, then when it hits Vref it will change state.   The opamp output is low so that's pulling the opamp +input down, so in order raise the opamp + input to Vref the input signal (VIN) must rise above Vref.    When that occurs the input voltage is at the upper Schmitt threshold VHI.

So with positive currents down the resistors the point where the opamp +input is at Vref requires,

(VHI - Vref) /47k =(Vref -VOL)/270k

Next is to do a brain switch.   Assume the opamp output is in high stable state and the voltage is VOH.   You go through the same type of thinking that the opamp +input must be high and the opamp output is high and you have a stable state.   To change the state the input voltage (VIN) need to decrease until the opamp +input drops to Vref.   Since the opamp output is high the only way that will happen is when VIN is below Vref.  That's the lower Schmitt input threshold VLO.

So now the opamp output is at VOH and current flows from the opamp output down the feedback resistor then down through the input resistor.   At the point where the opamp +input is at Vref, assuming all positive currents,

(Vref - VLO) /47k =(VOH -Vref)/270k

The key is to think of the voltages required to be in a stable state then think of the input going up or down and hitting the point which will change the state.    The point where the state changes is when the opamp inputs become equal, in your case when the opamp +input hits Vref.

Send:     . .- .-. - .... / - --- / --. --- .-. -
According to the water analogy of electricity, transistor leakage is caused by holes.

#### savethewhales

Quote
For more accurate results you can take into account the fact the opamp output doesn't swing 0V to VCC but swings approximately VOL=0V+1.5V = 1.5V to VOH = VCC-1.5V = 7.5V.

Yeeah I'm doing that.

Quote
It can be confusing analysing Schmitt trigger...
...in your case when the opamp +input hits Vref.

Ok sooo what you're saying is the state STARTS changing when +input hits Vref but FINISHES changing when the +input hits VLO?

It may not be what I'm saying, and if it's not, I wonder where do the VHI and VLO come into place here. Because as you mentioned the change starts at the Vref (which doesn't make sense because I have 2 thresholds designed for exactly this not happening.)

The op amp will try to equal the inputs all the time, as far as I am aware, right? If so, how come the non inverting input isn't always Vref?

Quote
(VHI - Vref) /47k =(Vref -VOL)/270k

This is what I didn't get. For me everything seemed clear, except for the fact that for the High threshold, we're doing calculations with the low output of the op amp...

I think I'm getting there, it's just a little bit more of something which I'm not getting.

#### Rob Strand

#149
QuoteThe op amp will try to equal the inputs all the time, as far as I am aware, right? If so, how come the non inverting input isn't always Vref?
No, it's not true.   This circuit is non-linear so it doesn't have to follow that rule.

There's two concepts you need to understand:
Opamp Saturation and Positive Feedback (and hysteresis)

Take an opamp without any feedback resistors or input resistors.  If we tie the opamp -input to Vref then when the opamp +input greater than Vref the opamp output will swing positive.   The opamp has a very large gain A  and the opamp output voltage tries to hit,

Vout = A * Vdiff
where,
Vdiff = "V at +input" - "V at -input".

If A is 100000 and power rail is 9V then with Vdiff = 1mV the opamp output tries to get to 100000*1mV = 100V but 100V is greater than the power supply voltage so the output get stuck at 9V.       We say the opamp saturates, or clips.     So what if we increase the input further to say  2mV, the output is still stuck at 9V.   In fact for any Vdiff  > +90uV   the output is stuck.  When we force the input like this the opamp +input does not have to match the opamp -input (=Vref).

When we have negative feedback the feedback resistor keeps Vdiff at 0V.    However we can still clip the opamp.  When clipping occurs the output will get stuck at 0V or 9V and Vdiff will actually become non-zero.  Negative feedback tries to make it zero but the clipped output stops that from occurring.

We can simplify the above for an ideal opamp with infinite gain that when Vdiff > 0 the opamp output saturates positively and gets stuck at the positive supply rail, and when Vdiff < 0 the opamp output saturates negatively and gets stuck at the negative supply rail.

The point here is the
- output stuck in saturation
- the input voltage can change without having an effect on the output.
- only Vdiff > 0 or Vdiff < 0 can change the output
(in you case think of opamp +input > Vref or opamp +input <  Vref)

QuoteOk sooo what you're saying is the state STARTS changing when +input hits Vref but FINISHES changing when the +input hits VLO?

...

It may not be what I'm saying, and if it's not, I wonder where do the VHI and VLO come into place here. Because as you mentioned the change starts at the Vref (which doesn't make sense because I have 2 thresholds designed for exactly this not happening.)

I understand where you are getting stuck.

The two thresholds come about because the opamp output voltage can be in two states (high and low).   The state moves the threshold.

When the output is stuck at 0V, there is a whole range of voltages where Vdiff < 0 and the output will stay stuck at 0V.    For example we can increase the input voltage from 0V to just under the threshold (VHI) and provided Vdiff is <  the opamp output will stay at 0V.   If Vdiff is just under 0V we can decrease the circuit input voltage again and Vdiff well got more negative and the opamp output doesn't change.

The threshold is the point where we change the output from 0V to 9V.    For that to happen Vdiff must increase from Vdiff < 0,  hit Vdiff = 0V, then when Vdiff is just above 0V the opamp output will swing to 9V.

Suppose we increase the circuit input so Vdiff just above zero.  In your Schmitt trigger the feedback resistor connects back to the opamp +input.   When the opamp output rise from 0V to 9V that resistor *increases* the voltage on the opamp +input.   So once you hit Vdiff > 0 the opamp drives *itself* harder into saturation.  This is called positive feedback.    Look what happens not if we back off the circuit input voltage.    The *circuit* input is currently at the threshold VHI.   If we try to decrease circuit input voltage like we did before  the output changed state we can't make Vdiff < 0.  The positive feedback as now "lifted" the opamp +input and made Vdiff *even more positive*.      So now if we want to make Vdiff < 0 we need to decrease the circuit input to less than the VHI threshold.    The new threshold is the VLO threshold.    The positive feedback changes the point where Vdiff hits zero depending on the voltage at the output of the opamp.

FWIW, the different threshold for increase and decreasing signals is called Hysteresis.  In order to get Hysteresis you need memory
which remembers the state.  In the case of a Schmitt-trigger the opamp output is remembering what state it is currently in.

This pic shows how the thresholds change depending on the (output) state.
[click to enlarge]

I strongly suggest using spice to look at the opamp +input on your Schmitt trigger.   There will be a triangle wave going up and down but there will also be up/down shifts in the opamp +input voltage.   The Schmitt trigger changes state when the opamp +input hits Vref.  However the change in the opamp output voltage raises and lower the opamp +input so the input needs to reach two different thresholds.

I don't know if this helps at all.   It can be a little tricky to understand.
Send:     . .- .-. - .... / - --- / --. --- .-. -
According to the water analogy of electricity, transistor leakage is caused by holes.

#### savethewhales

Quote
The point here is the
- output stuck in saturation
- the input voltage can change without having an effect on the output.
- only Vdiff > 0 or Vdiff < 0 can change the output
(in you case think of opamp +input > Vref or opamp +input <  Vref)

Ok, got it!

Quote
Suppose we increase the circuit input so Vdiff just above zero...
...The positive feedback changes the point where Vdiff hits zero depending on the voltage at the output of the opamp.

This is like when it reaches Vref, it goes even further positively, to the VUppertreshold? It makes sense.

Quote
I strongly suggest using spice to look at the opamp +input on your Schmitt trigger.   There will be a triangle wave going up and down but there will also be up/down shifts in the opamp +input voltage.   The Schmitt trigger changes state when the opamp +input hits Vref.  However the change in the opamp output voltage raises and lower the opamp +input so the input needs to reach two different thresholds.

Okkk understood. Here go the sims:

(click to enlarge)

So I'll try to draw some conclusion:
The output goes high, it's because the +input hit the Vref threshold. However, because it is on positive feedback, the input voltage (which is different from the +input) gets pushed to above Vref to a rate which depends on the resistor network put there. Is that it?
However I'm not getting why the +input gets pushed to even higher than the triangular wave itself.. wouldn't the triangle wave have that same peak?

Quote
I don't know if this helps at all.   It can be a little tricky to understand.

Helps even too much.
One thing is I understood the working of the Schmitt-Trigger circuit, and it's principle, however what I didn't understood was something specific about the final equation that you wrote down.

-> (VHI - Vref) /47k =(Vref -VOL)/270k

Again, we're doing calculations for the VHI (higher treshold), but taking into account the Low output VOL, why?
I thought since the VHI makes the circuit change output to VOH, what should be in the equation shouldn't be VOL but VOH in this case...

#### Rob Strand

QuoteThis is like when it reaches Vref, it goes even further positively, to the VUppertreshold? It makes sense.
Yes.   It moves up but not to  VUpperthreshold.  VUpperthreshold and VLowerthreshold only have meaning for the signal input node. The voltages at +input of the opamp have a different scaling to the signal input.   The important thing is the voltage moves up and down, it's not helpful think of amount the voltage changes at the opamp + input.    The other important thing is output changes state when the opamp +input reaches Vref.

QuoteHowever I'm not getting why the +input gets pushed to even higher than the triangular wave itself.. wouldn't the triangle wave have that same peak?
Suppose the input signal is at the peak of the triangle and the opamp out is at VOL.  The opamp +input reaches Vref, so the opamp output changes state from VOL to VOH.     When that happens the opamp +input *must* increase in voltage, because of the feedback resistor.  So that means the voltage must be higher than the triangle's peak.   Look at you sim, notice how the "shifted" triangles always aim *towards* Vref and the output changes state when it hits Vref.    It doesn't matter if the triangle is going up or down the signal on the opamp +input always aims at Vref.     The output changes can only occur when the opamp +input hits Vref.

QuoteOne thing is I understood the working of the Schmitt-Trigger circuit, and it's principle, however what I didn't understood was something specific about the final equation that you wrote down.

-> (VHI - Vref) /47k =(Vref -VOL)/270k

Again, we're doing calculations for the VHI (higher treshold), but taking into account the Low output VOL, why?
I thought since the VHI makes the circuit change output to VOH, what should be in the equation shouldn't be VOL but VOH in this case...

Check out this pic.   When we hit the upper threshold VUT, just before that the output is at -Vsat (which is VOL).     You can see the same effect for VLT, it depends on +Vsat (which is VOH).   When you look at the thresholds you need to think about what the opamp output level is upto now, not what it will changes to.

The way to think about is is while the output is at VOL,  the feedback resistor is pulled down, the opamp +input is pull down below Vref.   So in order to increase the opamp +input to Vref  then signal input must be higher threshold VHI (or VUpperthreshold or VUT).    Similarly if the opamp output is currently at VOH it's going to raise the opamp +input above Vref so in order to decrease the opamp +input the signal input must be the lower threshold VLO (or VLowerthreshold or VLT).
Send:     . .- .-. - .... / - --- / --. --- .-. -
According to the water analogy of electricity, transistor leakage is caused by holes.

#### savethewhales

QuoteIt moves up but not to VUpperthreshold...
... The output changes can only occur when the opamp +input hits Vref.

I guess you made it clear to me.. the noninverting goes up because of the feedback and to be able to return to Vref it needs a little help from the input voltage (which needs to reach VLT).

QuoteWhen we hit the upper threshold VUT, just before that the output is at -Vsat (which is VOL)...
... Similarly if the opamp output is currently at VOH it's going to raise the opamp +input above Vref so in order to decrease the opamp +input the signal input must be the lower threshold VLO (or VLowerthreshold or VLT).

Okk makes sense. I'm doing math for when I'm going to change to VUT and for that I must take into account that right before I change, I'm at -Vsat, right?

And for this situation I just wrote, the equation should be (VUT-Vref)/R14=(Vref-VOL)/R12 I assume?

#### Rob Strand

QuoteOkk makes sense. I'm doing math for when I'm going to change to VUT and for that I must take into account that right before I change, I'm at -Vsat, right?

Correct.

QuoteAnd for this situation I just wrote, the equation should be (VUT-Vref)/R14=(Vref-VOL)/R12 I assume?

Yep, that's it.
Send:     . .- .-. - .... / - --- / --. --- .-. -
According to the water analogy of electricity, transistor leakage is caused by holes.

#### savethewhales

Rob, I remember a while back when I was messing with the LFO and it was not working you advised me to use a non-polar capacitor instead of the polar cap I was using on the integrator (and was having bad results). In the end I changed it and it worked, but I don't really know how to explain why (because I think I don't even know). Could you explain that to me? Thanks!

Another thing is: I used two polarised caps in reverse series to substitute a non-polar cap (because I didn't have the value). But again, I don't know how this actually works and I've been searching for any literature/papers/trustworthy sites and I can't seem to find anything that explains to me why that works and why the total capacitance values (at low voltages) are 1/Ceq=1/C1+1/C2. Any help on this matter would be greatly appreciated.

#### Rob Strand

#155
QuoteRob, I remember a while back when I was messing with the LFO and it was not working you advised me to use a non-polar capacitor instead of the polar cap I was using on the integrator (and was having bad results). In the end I changed it and it worked, but I don't really know how to explain why (because I think I don't even know). Could you explain that to me? Thanks!

Another thing is: I used two polarised caps in reverse series to substitute a non-polar cap (because I didn't have the value). But again, I don't know how this actually works and I've been searching for any literature/papers/trustworthy sites and I can't seem to find anything that explains to me why that works and why the total capacitance values (at low voltages) are 1/Ceq=1/C1+1/C2. Any help on this matter would be greatly appreciated.
It not easy to explain.   Once you get past  1/Ceq=1/C1+1/C2 the explanation becomes very detailed and you need to know what happens inside the caps.

If you go here and read through articles 5 and 6 they cover some of the points.
https://linearaudio.nl/cyril-batemans-capacitor-sound-articles

Don't feel bad if you quickly feel like it's all to hard  .   You can just say it is/was a common method of making a bipolar capacitors from electrolytic capacitors.
Send:     . .- .-. - .... / - --- / --. --- .-. -
According to the water analogy of electricity, transistor leakage is caused by holes.

#### savethewhales

Quote
It not easy to explain.   Once you get past  1/Ceq=1/C1+1/C2 the explanation becomes very detailed and you need to know what happens inside the caps.

If you go here and read through articles 5 and 6 they cover some of the points.
https://linearaudio.nl/cyril-batemans-capacitor-sound-articles

Don't feel bad if you quickly feel like it's all to hard  .   You can just say it is/was common method of making a bipolar capacitors from electrolytic capacitors.

Ok, I've read some things, including the articles you put and I think i have an idea of how it works, I'll be writing what I know by now in my job.

Also, I read in the article 6 that the bipolar caps are done with two polar caps but in place of the
unformed cathode foil they use a second, formed, anode foil.

I actually quoted Cornel Dubilier in my job, which is the founder of CDE (they make capacitors for a big while now).

Anyway I'm not toooo worried but I would like to be able to explain at least a little bit of what's going on (if I'm asked to in my presentation).

Thanks

#### PRR

Quote from: savethewhales on October 27, 2020, 09:25:31 PMI actually quoted Cornel Dubilier in my job, .... Anyway I'm not toooo worried but I would like to be able to explain at least a little bit of what's going on (if I'm asked to in my presentation).

You might want to count and note the number of "L"s in Cornell, for formal work.

Dubilier was quite a guy. I have not found where Cornell comes in.
https://en.wikipedia.org/wiki/William_Dubilier
https://en.wikipedia.org/wiki/Dubilier_Condenser_Company

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