Help with the simulation of Phase 90 on LTSpice!!! JFET's giving 0.3 Volt sweep

[savethewhales]

The delays you are see are not realistic... That will start to change the frequency of the LFO a bit.

Ok. Yeah actually that was exactly what I simulated in the post above. greater values of Cap, worse edge of the wave.

Current doesn't come from R19.  R19 *determines* the voltages on the timing cap.  Current can come from the opamp output via R2 on your schematic (R36 on electrosmash link).

As an experiment try connecting a resistor (say the same size as R2 on your schematic) from the timing cap to ground and then to Vcc.   Notice how the cap voltage swings to the same peak voltages but on and off timing ratios are changed.

First sim gave me two equal results:





Gonna try to mess with the initial times (take them off):





I'm getting same responses.. I guess I'm doing it wrong then. Circuit:

The DC offset from the LFO can be a little confusing because it depends on how you look at it... In this region small changes in the gate voltage produce large changes in the JFET resistance.

When you said drain, you meant source, right?
Well, actually with the way that I'm biasing the whole thing, the average value of the LFO output is at 4.65 V, almost Vref which stays at around 4.8.

As for the jFET resistance, that part i'll be honest and say that I understood already, I even designed the circuit (to simulate) in a way that the lowest voltage that goes to the gate, can pass downwards the lowest possible (3.5 Volt in my case because I have my FET's at a VGS-off of 1.3 V), as the 22k in parallel makes it not change too much above it. However, I designed it to not pass 4.6 Volt upwards of gate input, meaning that It doesn't pass -0.2 VGS upwards, because I would have way too low resistance value, meaning a cutoff frequency of above 20k Hz (which i'm not interested at all).
I calculated the resistance as being 432 ohms, but there's no way to calibrate the circuit other than at eye, when I'm beside an oscilloscope.

[Rob Strand]

First sim gave me two equal results:

Gonna try to mess with the initial times (take them off):

I'm getting same responses.. I guess I'm doing it wrong then. Circuit:

The added resistor doesn't connect in series with cap.    The added resistor connects to the upper side of the cap then to Vcc or gnd. The purpose of the exercise is to show that if you put current in or draw current out of the LFO output (ie. at the cap) it affects the LFO duty cycle but does not affect the output swing.        It's not an improvement or mod.  It shows what happens when you load down the LFO.

When you said drain, you meant source, right?

Yes, sorry about that.

Well, actually with the way that I'm biasing the whole thing, the average value of the LFO output is at 4.65 V, almost Vref which stays at around 4.8.

As for the jFET resistance, that part i'll be honest and say that I understood already, I even designed the circuit (to simulate) in a way that the lowest voltage that goes to the gate, can pass downwards the lowest possible (3.5 Volt in my case because I have my FET's at a VGS-off of 1.3 V), as the 22k in parallel makes it not change too much above it. However, I designed it to not pass 4.6 Volt upwards of gate input, meaning that It doesn't pass -0.2 VGS upwards, because I would have way too low resistance value, meaning a cutoff frequency of above 20k Hz (which i'm not interested at all).
I calculated the resistance as being 432 ohms, but there's no way to calibrate the circuit other than at eye, when I'm beside an oscilloscope.

In spice you can measure the minimum LFO voltage then replace the LFO with a fixed voltage of that value and look at the response.   As for the real device, yes, it's tricky setting-up the circuit because the LFO is modulating all the time.  Most people set it up by ear.

[savethewhales]

...the zener voltage is 4.8V and not the 5.1V on the label.  ... problem of having an exact zener model with a 10k resistor to 9V, which is going to give you 4.8V anyway!

Yes, don't trust SPICE at all, or its models.

The "sag" of Vz at low currents is 'normal' of course; philosophically it must go to zero at zero current, and there may be no "magic current" where it jumps-up to rated value.

Curious, I plotted the one Zener in my spice. (Yes, a 4.7V breakover is different from a >7V breakover.) At 0.4mA (9V through 10K) it reads a little low, though not as low as is reported for P90s.

Guys I'm sorry for bringing this here now after that much time, but where does the 0.4 mA come from? The 9V with the 10k resistor isn't supposed to give 0.9 mA?

Thanks

[savethewhales]

So, I've started to simulate the LFO together with the power supply in the circuit, and I've noticed that the real circuit gives at the gates of the FET's a wave that is way less triangular than supposed (even with tweaking the cap that sets the edges of the wave). The simulations (with explanation), come below.
This is what i'm getting:

                  Resistance          Connection
1 -                 1Meg             Power Supply
2 -               2.7 Meg           Power Supply
3 -                 1Meg         4.8 Volt Source (simulating Zener Volt.)
4 -               2.7 Meg       4.8 Volt Source (simulating Zener Volt.)









Does anyone have any guess on why this is happening? Thanks.

[PRR]

> The 9V with the 10k resistor isn't supposed to give 0.9 mA?

9V at one end, 5V at the other end. 4V difference.

[savethewhales]

> The 9V with the 10k resistor isn't supposed to give 0.9 mA?

9V at one end, 5V at the other end. 4V difference.

Ok, true!

[savethewhales]

The added resistor doesn't connect in series with cap.    The added resistor connects to the upper side of the cap then to Vcc or gnd. The purpose of the exercise is to show that if you put current in or draw current out of the LFO output (ie. at the cap) it affects the LFO duty cycle but does not affect the output swing.        It's not an improvement or mod.  It shows what happens when you load down the LFO.

The sims go below:

Circuit:


R36-Vcc


R36-Ground


I'm afraid I coudn't take a conclusion out of these sims.

In spice you can measure the minimum LFO voltage then replace the LFO with a fixed voltage of that value and look at the response.   As for the real device, yes, it's tricky setting-up the circuit because the LFO is modulating all the time.  Most people set it up by ear.

Yeah! I was doing that before!

Now I'm actually using the normal circuit and putting a initial condition which reflects the voltage that I want to look at (hint: it works).

When i'm with an oscilloscope I guess it'll be easier for me to set up things.

With the sims I'm doing, I'm seeing that the Rds is changing drastically near the Vgs-off point, meaning that it reaches hundreds of ohms (500 below with my calculations) pretty darn fast, which if it was real (not just the simulation), it would leave me with a very poor voltage span (I was thinking 1.1 Voltage span for my -1.3 VGS-off jFETS, but I would have to have something like a 0.3 Voltage span because of the rate of change of rds).

Do you think this is normal in the physics of the component or is it something that can happen due to simulation/approximations/models?   

Thanks Rob

[savethewhales]

Something curious:

With this circuit (almost equal to the Phase90 LFO):



I did a transient analysis, to see the voltages at every node since the potentiometer of Bias.
The result is this:



Which in my conclusion means that the voltage in the output of the trimmer is not fixed, and the LFO only works because of that change. In this case I guess I can conclude that theres more than one feedback loop in this circuit, which seems really hard to understand and calculate.. 

[Rob Strand]

With the sims I'm doing, I'm seeing that the Rds is changing drastically near the Vgs-off point, meaning that it reaches hundreds of ohms (500 below with my calculations) pretty darn fast, which if it was real (not just the simulation), it would leave me with a very poor voltage span (I was thinking 1.1 Voltage span for my -1.3 VGS-off jFETS, but I would have to have something like a 0.3 Voltage span because of the rate of change of rds).

Do you think this is normal in the physics of the component or is it something that can happen due to simulation/approximations/models?

Normally you see Rds *increasing* more rapidly as you approach Vgs_off.   The drain resistance is,

    rds =   rds0 / (1 - |Vgs|/|Vp|)   ; where rds0 = 1/Yfs0 and is typically around 200 ohms

The resistor (20k to 30k) in parallel  with the JFET limits the rise.

For a typical vintage phaser the JFET rds is probably around 10k ohm to 12k ohms.   So if you reverse that calculations that means |Vgs|/|Vp| is 0.98.   2% error of adjustment in Vbias will give |Vgs|/|Vp|=0.96 and that is going to drop rds to 5k ohms.   So 2% adjustment error is causing 100% change.     It's extremely sensitive.

It's unlikely you will be able to eye-ball the oscilloscope voltage and transfer them to spice.   Also the real JFETs have different Vgs_off and that's not be taken into account in spice.

That's why I suggest adjusting the real unit by ear.   However for spice you are best working out the Vgs required to get rds=10k then setting the minimum voltage of the LFO to that number.

Which in my conclusion means that the voltage in the output of the trimmer is not fixed, and the LFO only works because of that change. In this case I guess I can conclude that theres more than one feedback loop in this circuit, which seems really hard to understand and calculate.. 

You need to think of the Vbias source as a Thevenin equivalent circuit.   The bias trimpot provides a variable voltage source but the trimpot resistance means the Vbias source has a output impedance (perhaps around 50k ohm).   When you probe the trimpot wipe you are probing at the output side of that 50k source impedance.  In practice the 50k adds to the 1M resistor in series with the trimpot wiper so it actually ends up having little effect.    If you want to check things from theoretical point of view you can replace thr trimpot with a fixed voltage source in series with say 50k but now can probe both sides of the 50k resistor.

[savethewhales]

Normally you see Rds *increasing* more rapidly as you approach Vgs_off.   The drain resistance is,

    rds =   rds0 / (1 - |Vgs|/|Vp|)   ; where rds0 = 1/Yfs0 and is typically around 200 ohms

The resistor (20k to 30k) in parallel  with the JFET limits the rise.

Thanks for the insight.

Knowing that I cannot exceed 417 ohm downwards, I did some calculations:

if rds0 (i suppose it's rds on) is 200 (minimum on the 2n5457), within -1.2 and -1.29 vgs (-1.3 Vpinch) I get between 2.5 k and 26 kohm. This now makes sense. Also, for me to get the jFET resistance to 417 ohm (for the notches to not exceed 20kHz), I get -0.676 vgs.

If rds0 is 333 middle case, for me to get the jFET resistance to 417 ohm, vgs is -0.26 V. 

Last case is rds on 1khz (max) and I don't even have to worry about the notches, because they won't reach near 20kHz.

So if I get rdson below 417 ohm is when I need to worry, and think about diminishing the voltage span or putting a series resistance with the drain.

For a typical vintage phaser the JFET rds is probably around 10k ohm to 12k ohms.   So if you reverse that calculations that means |Vgs|/|Vp| is 0.98.   2% error of adjustment in Vbias will give |Vgs|/|Vp|=0.96 and that is going to drop rds to 5k ohms.   So 2% adjustment error is causing 100% change.     It's extremely sensitive.

It's unlikely you will be able to eye-ball the oscilloscope voltage and transfer them to spice.   Also the real JFETs have different Vgs_off and that's not be taken into account in spice.

That's why I suggest adjusting the real unit by ear.   However for spice you are best working out the Vgs required to get rds=10k then setting the minimum voltage of the LFO to that number.

You say maximum rds? Or do you say rds that is equivalent to the parallel? I didn't get it. However, I understand the idea behind what you're saying. Subtle changes may be = big changes.

I'm thinkin about setting up my circuit in a way that the only preocupation I would have would be the lowest rds possible (which I already calculated as 417 ohm). If the frequency response gives me more than 20k of notch, then I will have a problem and I will want to solve it. 

As I'm putting on the sims on this post, I am yes calculating the values of the LFO to give me exactly what I want (and I was able to get 1.1 Volt Span on LFO), but it isn't worth it when I know in real life there will be drastical differences (vgs off not equal tween jfets; yfs not equal tween jfets; no practical way to change resistors in a fast time; having to simulate the phasing part with a voltage source instead of the LFO, etc).

You need to think of the Vbias source as a Thevenin equivalent circuit.   The bias trimpot provides a variable voltage source but the trimpot resistance means the Vbias source has a output impedance (perhaps around 50k ohm).   When you probe the trimpot wipe you are probing at the output side of that 50k source impedance.  In practice the 50k adds to the 1M resistor in series with the trimpot wiper so it actually ends up having little effect.    If you want to check things from theoretical point of view you can replace thr trimpot with a fixed voltage source in series with say 50k but now can probe both sides of the 50k resistor.

Ok this is great, I just wanted to be able to explain this theoretically. I don't understand the meaning/importance of the impedance here. Well actually maybe I do. The "50k" adds to the 1megaohm, in that way what I dd in my sims above is correct, probed the trimpot with 50k and then to the right of 1mega, which is node Vbias.

However how does this all apply to it's function of the LFO? How could I calculate this? The LFO input is a divider from the LFO out and the Vbias +50k+1mega right? If so, the vbias has a weight of 50k+1mega and the lfo out has a weight of 3.9 mega? And how does the Vbias oscillate?

Tomorrow as soon as I can I will simulate the trimpot as a source with 50k and put results here.

Sorry for all questions but the LFO is tripping me out already. 

[Eb7+9]

So if I get rdson below 417 ohm is when I need to worry, and think about diminishing the voltage span or putting a series resistance with the drain.

in a normally operating unit you won't be using the full resistive range of the jFET,
and not all the way down to that end either ... so, no need for padding at the drain

the question is, how much relative Cv range is enough here?

with a fixed (300mVpp) control signal swing one would expect the stock P90 LFO circuit to have a much stronger effect operating on lower-Vp devices rather than on higher-Vp ones ... a never-mentioned key player in the variance of the overall response

as a silly/extreme example, if you could somehow manage to find yourself four matched jFETs with their Vp's measuring -0.30 volts you would then theoretically have a stock P90 running at 100% max Depth ... with absolutely no guarantee that it would sound good or useful either

conversely, the P90 LFO can be modded for higher or lower Cv swing ... though, if the common approach (variable loading) is done on the stock circuit then each time the load is adjusted the BIAS trim may need to be re-calibrated in order to regain an even sweep ...

for a more perfect (bias invariant) DEPTH control the whole circuit needs to be re-arranged slightly, with an extra op-amp likely needed ...

[savethewhales]

Did the sim without the 250k trimpot but with a source and the respective resistance (3.618 V and 62.5k as I had on my circuit), and I was able to look at the voltages that are around the resistors, and the voltage dividing they do:





As I can see, the voltage at the 62.5k resistor oscillates a bit, and it's surely making a (really small) difference in the LFO/Vgates. Anyway, I would like to be able to control things to my taste, but it seems I need a little bit of calculations with this (which I've tried but cnnot understand fully).

[savethewhales]

in a normally operating unit you won't be using the full resistive range of the jFET,
and not all the way down to that end either ... so, no need for padding at the drain

Yes, with the sims I understood that I don't even want to get to 0 vgs (it would even be bad for me). However, the pad is just to NOT pass that limit resistance, but yes if I desgin the circuit not to pass it, no need for pad (even though I was thinkin would be the simplest).

the question is, how much relative Cv range is enough here?

with a fixed (300mVpp) control signal swing one would expect the stock P90 LFO circuit to have a much stronger effect operating on lower-Vp devices rather than on higher-Vp ones ... a never-mentioned key player in the variance of the overall response

as a silly/extreme example, if you could somehow manage to find yourself four matched jFETs with their Vp's measuring -0.30 volts you would then theoretically have a stock P90 running at 100% max Depth ... with absolutely no guarantee that it would sound good or useful either

Well, I understand that a CV of vgs-off to more or less 417 ohm rds would be enough for me!

That P90 case is very true and strange. But I was thinkin and I think they do it like that really because the resistance changes so much near the vgs-off point, that you would be "good" having 0.3V p-p span, because your rds would change a lot (maybe not as much as you would want/idealize. Because of this very fact, and some others, is why I am trying to design something slightly different.

conversely, the P90 LFO can be modded for higher or lower Cv swing ... though, if the common approach (variable loading) is done on the stock circuit then each time the load is adjusted the BIAS trim may need to be re-calibrated in order to regain an even sweep ...

for a more perfect (bias invariant) DEPTH control the whole circuit needs to be re-arranged slightly, with an extra op-amp likely needed ...

When you say variable loading, you mean changing the 1M resistor and the "depth" pot that I have on the schematic? If so, yes I was changing it together with the bias trimmer, because or it was getting an offset upwards or downwards (if I remember correctly), and the solution was to change the bias trimmer at the same time.
This actually started with me trying to reach the lowest voltage of the LFO as being 3.5 Volt (3.5-4.8=-1.3 Volt pinch off), but I haven't made too much of calculations because I don't understand how they would work here. For me it was a matter of trying/error/luck.

It interests me of having a rearrangement of the circuit with an extra op-amp. What did you thought of? Putting an op amp in the out of the 1M ohm resistor? Or for something completely different?

Thanks,

Fred

[Rob Strand]

You say maximum rds? Or do you say rds that is equivalent to the parallel? I didn't get it.

The values are for the rds of the JFET.   The parallel fixed resistor will drop the total resistance.

However how does this all apply to it's function of the LFO? How could I calculate this? The LFO input is a divider from the LFO out and the Vbias +50k+1mega right? If so, the vbias has a weight of 50k+1mega and the lfo out has a weight of 3.9 mega? And how does the Vbias oscillate?

As I can see, the voltage at the 62.5k resistor oscillates a bit, and it's surely making a (really small) difference in the LFO/Vgates. Anyway, I would like to be able to control things to my taste, but it seems I need a little bit of calculations with this (which I've tried but cnnot understand fully).

You should be able to see why from your simulation.    In the simulation the Thevenin voltage is now Vbias and it doesn't fluctuate but the output terminal at the other side of the 62.5k does fluctuate.   When you use a trim pot the *open circuit* voltage of the pot is the Vbias in the simulation;  that's how you define the Thevenin voltage.    However with a trimpot you can see the "internal" Vbias point you only see the output terminal which is the side of the 62.4k that fluctuates.

Yes, the fluctuation is small.   Its effect is small because 62.5k is much smaller than 1MEG.

 

[savethewhales]

The values are for the rds of the JFET.   The parallel fixed resistor will drop the total resistance.

So you mean the Typical vintage phaser has a parallel resistor of 10-12k?

You should be able to see why from your simulation.    In the simulation the Thevenin voltage is now Vbias and it doesn't fluctuate

Ok

but the output terminal at the other side of the 62.5k does fluctuate. 

Yes!

When you use a trim pot the *open circuit* voltage of the pot is the Vbias in the simulation; 

Okay

that's how you define the Thevenin voltage.    However with a trimpot you can see the "internal" Vbias point you only see the output terminal which is the side of the 62.4k that fluctuates.

Can't, right?
Yes I got that. But the whole question of mine, is how I'm gonna do the calculation, do you understand? Like, how is the voltage coming from the LFO to the 62.5 k resistance? it's something that is bugging me.

Yes, the fluctuation is small.   Its effect is small because 62.5k is much smaller than 1MEG.

Yeah it does make sense actually! I just have to understand how and why the LFO out goes into the 62.5k and the 1Mega.. Is it because the schmitt trigger needs an oscilation? If so, how is this working in the circuit I put above?

[Rob Strand]

So you mean the Typical vintage phaser has a parallel resistor of 10-12k?

The *JFET* is 10k to 12k.   The circuit will have an additional resistor in parallel with the JFET (typ. 20k to 30k).  So the combination will produce a maximum resistance of  8k or so.

Yes I got that. But the whole question of mine, is how I'm gonna do the calculation, do you understand? Like, how is the voltage coming from the LFO to the 62.5 k resistance? it's something that is bugging me.

It's just the Thevenin equivalent circuit of the bias trimpot.   It's not a precise value because it depends where the pot is set.   The precise method would be to adjust the trimpot then measure the wiper to top-terminal resistance and wiper to bottom-terminal resistance then the Thevenin equivalent impedance is the parallel combination of the two.      The ball-park way is to say the pot is 0 ohms at the top and bottom.  In the middle it's Rpot / 4 = 250k /4 = 62.5k.  So on average it's (62.5k + 0) /2 = 31k.

The whole idea of accounting for the trimpot resistance is that you *know* it has an effect.   The effect is small, so throwing in a ball-park estimate just pushes and calculations closer to reality.    I do often account for this type of thing because the measurements and calculations don't have a built-in approximation bias.

In the light of not accounting for the JFET's having different Vgs_off it is a small contribution.

Yeah it does make sense actually! I just have to understand how and why the LFO out goes into the 62.5k and the 1Mega.. Is it because the schmitt trigger needs an oscilation? If so, how is this working in the circuit I put above?

The reason is it provides a way for the DC bias and the LFO output to be combined; based on the k factor thing I posted previously.  That's what the JFET needs.

The 1M works with the 3M9 resistor to  divide down the LFO swing.


You could design the circuit to remove the 1M and 3M9 then design the LFO to have the correct DC offset and LFO swing for the JFETs.    If you did that you would find is (if you tried to use a similarly simple circuit),

- The DC bias would vary more when the 9V rail varied.   Keep in mind the 9V supply isn't regulated and the these pedals operated off battery, which could vary from say 7V to 10V.

-When you adjusted the DC bias it would affect the LFO duty-cycle and frequency.

As it is the circuit tries to separate the LFO and JFET DC biasing as much as possible.    The Vbias from the bias trimpot is mostly determined by the zener voltage, which is relatively independent of the supply.      The DC variations from the LFO is kept to a minimum.  The guys that designed the LFO designed it like they did because they did consider these factors.   From a design point of view, I know the problems that need to be addressed and I can see their design addressed those problems as far a practically possible using fairly common circuit building-blocks.    That doesn't mean there aren't other ways to do it!

[savethewhales]

The *JFET* is 10k to 12k.   The circuit will have an additional resistor in parallel with the JFET (typ. 20k to 30k).  So the combination will produce a maximum resistance of  8k or so.

Ok!

It's just the Thevenin equivalent circuit of the bias trimpot.   It's not a precise value because it depends where the pot is set.   The precise method would be to adjust the trimpot then measure the wiper to top-terminal resistance and wiper to bottom-terminal resistance then the Thevenin equivalent impedance is the parallel combination of the two.

Ok!

The ball-park way is to say the pot is 0 ohms at the top and bottom.  In the middle it's Rpot / 4 = 250k /4 = 62.5k.  So on average it's (62.5k + 0) /2 = 31k.

Wait, why Rpot/4?

The whole idea of accounting for the trimpot resistance is that you *know* it has an effect.   The effect is small, so throwing in a ball-park estimate just pushes and calculations closer to reality.    I do often account for this type of thing because the measurements and calculations don't have a built-in approximation bias.

Hmm okay. It's true. But in my case I want it to be exact. I know the exact caractheristics of the matched jFET's so I wanted to build based on that. That is why I was choosing those values on my circuits on Spice.

The reason is it provides a way for the DC bias and the LFO output to be combined; based on the k factor thing I posted previously.  That's what the JFET needs.

You mean they do an "adder circuit" too? And that's because the LFO needs an "input oscillation" right?

The 1M works with the 3M9 resistor to  divide down the LFO swing.

Yes.

You could design the circuit to remove the 1M and 3M9 then design the LFO to have the correct DC offset and LFO swing for the JFETs.    If you did that you would find is (if you tried to use a similarly simple circuit),

- The DC bias would vary more when the 9V rail varied.   Keep in mind the 9V supply isn't regulated and the these pedals operated off battery, which could vary from say 7V to 10V.

Hmm why? I would really like to do that, and in this case, use a 9V power supply only. How can I do what youre saying?

-When you adjusted the DC bias it would affect the LFO duty-cycle and frequency.

Hmm.. I would like to see and simulate the circ.

As it is the circuit tries to separate the LFO and JFET DC biasing as much as possible.    The Vbias from the bias trimpot is mostly determined by the zener voltage, which is relatively independent of the supply.

Yes.

The DC variations from the LFO is kept to a minimum.  The guys that designed the LFO designed it like they did because they did consider these factors.   From a design point of view, I know the problems that need to be addressed and I can see their design addressed those problems as far a practically possible using fairly common circuit building-blocks.    That doesn't mean there aren't other ways to do it!

That's where I wanted to get. I wanted to do something quite different and exclusive to the caractheristics of FET's that I have. My problem is, as far as I'm concerned, I need the input to oscillate, as I mentioned before, and I know the P90 circuit has the input on the LFO oscillated by what you explained (even though I don't understand exaaactly how they do it).

Either way i'm starting to think this thread is going too big for casual readers, and I would ask if I can contact you privately.. If so, how?

Thanks and regards.

[11-90-an]

It’s ok fir a thread to be long, as long as it isn’t a popcorn thread...

You can Private Message (PM) by going to the “my messages” and sending messages to any forumite.

I’m sure other people can learn from this thread. Don’t worry! 

It’s still 4 pages long. Still kinda short compared to deadastro’s threads... 

[savethewhales]

It’s ok fir a thread to be long, as long as it isn’t a popcorn thread...

You can Private Message (PM) by going to the “my messages” and sending messages to any forumite.

I’m sure other people can learn from this thread. Don’t worry! 

It’s still 4 pages long. Still kinda short compared to deadastro’s threads... 

Hahah ok, thanks! I actually tried to contact Rob with PM but not answered yet. I hope to be saying relevant things in this thread!

[Rob Strand]

Wait, why Rpot/4?

If you set the pot to half-way there is Rpot/2 from the wiper to one end and Rpot/2 from the wiper to the other end.  Thevenin equivalent resistance is those two in parallel so Rpot /4.

You mean they do an "adder circuit" too? And that's because the LFO needs an "input oscillation" right?

Yes it does add the DC from the trimpot with the LFO.

Hmm why? I would really like to do that, and in this case, use a 9V power supply only. How can I do what youre saying?

The MXR circuit is already doing that.    If you want to see how the circuit performs run you spice simulation with the at 9V and at 7V and look at what happens to the LFO.   In this case you might want to reduce the voltage of the zener when at 7V because in reality the zener voltage will drop.


The other thing you can do is compare two designs.  You set-up the two circuit to be equivalent at 9V then you change the supply to 7V and look at how the gate voltage is changes.  One will change less than the other.

That's where I wanted to get. I wanted to do something quite different and exclusive to the caractheristics of FET's that I have. My problem is, as far as I'm concerned, I need the input to oscillate, as I mentioned before, and I know the P90 circuit has the input on the LFO oscillated by what you explained (even though I don't understand exaaactly how they do it).

Either way i'm starting to think this thread is going too big for casual readers, and I would ask if I can contact you privately.. If so, how?

Unfortunately coming up with a better design is a whole project in itself.     There's many ways to do it.   A very simple way to make the circuit tougher against supply variation is simple to regulate the power supply!   Ideally you would want to regulate the supply without lowering the headroom of the audio circuits.