Author Topic: Help with the simulation of Phase 90 on LTSpice!!! JFET's giving 0.3 Volt sweep  (Read 11263 times)

savethewhales

Guys Just an update: I measured the VGSoff of the JFET's I got, and here are the values (I used 3.9 Megaohm resistor):

1: 1.245 V
2: 1.241 V
3: 1.270 V
4: 1.271 V

The factor of multiplication is somewhere around 1.85 from what I measured with the R.G Keen test. I guess I couldn't do it without you guys.

Another thing is, the biggest difference in VGSoff stays at 2.4%. Is it reasonable? Or for paying 8.5 Euro for a matched set I would expect better?

Thanks, Fred

Rob Strand

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Another thing is, the biggest difference in VGSoff stays at 2.4%. Is it reasonable? Or for paying 8.5 Euro for a matched set I would expect better?
Anything better than 50mV is quite good.
Yours are 30mV worst case, so that's pretty good.
Plopping around the pot since an early age.

savethewhales

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The general idea is covered here...
... just as you don't need to add .lib or .inc for the "builti-in" LTspice parts”

I followed the website and was able to add a model, thanks!
Nice explanation of your parts, I’ve already wrote down what you said here, if I will use it in the future.

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They are only wrong if you interpret them as VGS_off... using the correction factor I calculated (or one like it).

Yeah, I understand now! Those values (R.G.) seemed right, because I saw that they were close to each other (but at the same time thought it was strange to get -0.7V VGSoff). But now I understand (thanks to you) that it’s wrongly said VGSoff. So I would say that the real and best test would be the one you showed me, cause there’s no reason to use the other.

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OK I get it... I just do it less often.

Yeah, I actually got happy to be able to interpret the results and see that “no matter the input” the gain won’t change. The why’s for the +5dB stays for other time.
I imagine frustration and problems will never disappear, as you might be the proof of that (as you’re telling me, not that I'd have anything close to your experience).

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So the main problem is if you *never* check against reality you are just seeing numbers on the computer... When you plop down a whole heap of ICs with unverified models the results are hit and miss.”

Pretty interesting… It makes all sense. With the LFO I actually am testing it alone (separated from the circuit) because spice doesn’t do real time analyser as I’m aware (so I couldn’t see the notches moving), but now I have even other reasons. Oh and when I want to use the “LFO voltage” in my circuit I change the bias voltage, in that way it’s like the LFO was moving (or some place in the up’s/downs of the wave).

I did Zener=4.8V source because what I wanted to test wasn’t the power stage of the circuit but the LFO/Phasing part.
Also, I was thinking bout doing 555 in my circuit (as the comparator with the square output), but I don’t know quite well how to use it… Either way, a very good idea would be to use a square wave generator as you mentioned it. Surprisingly, I was thinking bout asking here: Do you think it’s a good idea to substitute the “obsolete” P90 triangular wave LFO for a 555 timer with na integrator? Or is there any significant drawback? My reasons would be because I searched and talked to some people who highly instructed me to use the 555.

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There's a few sites on the web about converting datasheets to spice models

Pretty interesting… Wrote down.

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Slope is about how well the Zener regulate, which is kind of it's job... but at least one which will match the circuit you build.

I imagine that… It’s few information, which they are allowed to only give to be able to sell, if not, there’s plenty of others saying that “they do better”.

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A lot of parts are not precisely defined... but then you need to make sure the circuit at least works with high and low gain cases.”

This.. seems to be very important. As long as we know what to change in the model (to make it the worst or best scenarios), we should really do that testing of best/worst case.

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You can go a long way with ignorance is bliss philosophy but one day it will catch up with you.

Won’t forget this… Won’t forget…

savethewhales

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Same thing either way... Easy to compute but physically unlikely.

Yeah, seing it in LOG "looked like" the datasheets, meanwhile the LIN really shows some crappy moddeling (I would guess). But I don't know already, if that works for the current I wanted, that's alright, if not, i'll find a voltage source and done...

savethewhales

Anything better than 50mV is quite good.
Yours are 30mV worst case, so that's pretty good.

Nice!!!!! I'm expecting now another set of JFET's (because they just didn't arrive) and then I'm gonna probably choose the closest matches/bigger VGSoff possible.

Rob Strand

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Also, I was thinking bout doing 555 in my circuit
Opamps are probably better as you can slow-down the switching transitions and they don't have strong current pulses on the supply rails.   NE555's + audio need extra care.
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Nice!!!!! I'm expecting now another set of JFET's (because they just didn't arrive) and then I'm gonna probably choose the closest matches/bigger VGSoff possible.
If you can get below 50mV it will sound right for sure.   

JC Maillet (user E7b9) had some stuff on his web-site which lets you use mismatched JFETs.   You add a bias pot to each JFET.  It's more mucking about to adjust but it lets you use any old JFETs.    You can even use a simplified version where you split the JFETs into two sorted groups: low Vgs_off and high Vgs_off.   Then only have two trimpots to adjust (assuming the parts in each group are relatively close).
Plopping around the pot since an early age.

savethewhales

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Opamps are probably better as you can slow-down the switching transitions and they don't have strong current pulses on the supply rails.   NE555's + audio need extra care.

Hmm. interesting. What does the strong current pulses could cause? Easily fried resistors i guess? Cause I talked to a guy who works in building effect modules and stuff, and he explained me that the op-amp as I was using (in the triangular wave LFO) was not giving me exact square form wave, neither exact triangular form, and never would. Besides that, he said that the circuit has too much feedback, and the input of the op-amps, being BJT's, would oscilate too much and become unstable.. Does this make any sense?   

If so, how bout the lm339? For audio it should make sense, right?

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If you can get below 50mV it will sound right for sure... Then only have two trimpots to adjust (assuming the parts in each group are relatively close).

Could you write me the website? Or if you want, by message, I don't know.

Anyway, it could be a veery good idea to have pots to each JFET. As I already have a matched set, I don't think I will need to do it, yet.

...

Given all that, I already saw so much about the LFO's and studied about schmitt trigger, but I'm thinking it's a bit too complex for me to understand the schematics of the LFO on the Phase 90. It's like I get the idea, but the function of each resistor and how the op-amp part operates is something I'm not getting right.
One of the reasons for me wanting to change to a comparator is that. I don't seem to be confident enough to explain the operaton of the TL072 there it in a final presentation of college, as I don't exactly know what it does. Follows down the LFO schematic I'm refering to:





Rob Strand

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What does the strong current pulses could cause?
You get clicks in the audio at the LFO rate.  Some opamp designs do that.

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If so, how bout the lm339? For audio it should make sense, right?
You can only try it.  You should be able to get it to work.  Comparators usually have faster edges than opamps so there is more chance for the sharp transistions to get into the audio.   The slow opamps tend to be slow by nature.

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Could you write me the website? Or if you want, by message, I don't know.

Anyway, it could be a veery good idea to have pots to each JFET. As I already have a matched set, I don't think I will need to do it, yet.
It's here.  This method offers the  best results for mismatched JFETs.   However if your JFETs are reasonably matched you don't need to go so far.
https://viva-analog.com/viva-analog-paradigm-shifter-jcmc-2017/

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Given all that, I already saw so much about the LFO's and studied about schmitt trigger, but I'm thinking it's a bit too complex for me to understand the schematics of the LFO on the Phase 90. It's like I get the idea, but the function of each resistor and how the op-amp part operates is something I'm not getting right.
One of the reasons for me wanting to change to a comparator is that. I don't seem to be confident enough to explain the operaton of the TL072 there it in a final presentation of college, as I don't exactly know what it does. Follows down the LFO schematic I'm refering to:

Go here, go to the bottom of the page,

https://www.electrosmash.com/mxr-phase90

R19 and R21 set the upper an lower threshold of Schmitt trigger.  One threshold when the opamp output is high an one when it is low.  You use the voltage divider equation with R19 and R21 to get the voltage on U1b's + input.    When the cap voltage reaches one of those thresholds the output of the opamp changes state.   That causes the cap to charge or discharge in the opposite direction until it hits the other threshold.

For understanding, ignore C7 and R24, their purpose is to slow down the transistions which helps avoid clicks.  They to affect the behaviour a little bit.

The trimpot set the DC level to the JFETs.

The 3M9 resistor and the 1M resistor (+added trimpot) mix the DC from the trimpot and the LFO output.

From the perspective of the JFET gates, the 1M(+added trimpot) doesn't affect the DC level so much.   However for the LFO, the 1M(+added trimpot) form a divider so when the trimpot is set to a low value it reduces the amount of LFO signal getting to the gates.  Similarly when the trimpot is  set to a high value the divide lets more LFO signal through to the gates.

A small detail is the LFO waveform is a "triangular" waveform plus a DC offset of about 4.5V.  That comes about because the circuit is single supply.   The DC offset does have an effect on the JFET biasing.   The bias trimpot has enough adjustment to factor in that fixed DC component.
« Last Edit: September 16, 2020, 12:52:03 PM by Rob Strand »
Plopping around the pot since an early age.

savethewhales

The get clicks in the audio at the LFO rate.  Some opamp designs do that.

Wow this would be really bad..

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You can only try it... The slow opamps tend to be slow by nature.

Yeah, I would have to try it in physical reality. So between TL072, LM393/339 and NE555 you would reccomend better the TL072 right?

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It here...
https://viva-analog.com/viva-analog-paradigm-shifter-jcmc-2017/

Thank you. Already took a look at it seems a endless fountain of information for me.

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R19 and R21 set the upper an lower threshold of Schmitt trigger.  One threshold when the opamp output is high an one when it is low.  You use the voltage divider equation with R19 and R21 to get the voltage on U1b's + input.   


Ok, fair enough! What do you mean by voltage divider equation with R19 and R21? How do you come to that equation?

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When the cap voltage reaches one of those thresholds the output of the opamp changes state.   That causes the cap to charge or discharge in the opposite direction until it hits the other threshold.

Alright, that I can deal with. But we're talking about the C10, right?
And, I know you said to ignore C7 and R24, but how do they prevent those clicks? I can't see how..

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From the perspective of the JFET gates, the 1M(+added trimpot) doesn't affect the DC level so much.   

What do you actually mean? Because the 1M+trim will give the DC "level" necessary to make the FET's vary, in other words, will deliver voltage to the gate of the FET's, right? So how can it not affect level?

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However for the LFO, the 1M(+added trimpot) form a divider so when the trimpot is set to a low value it reduces the amount of LFO signal getting to the gates.  Similarly when the trimpot is  set to a high value the divide lets more LFO signal through to the gates.

I don't quite understand it.. It seems to me that what one would want would be that the LFO came to the gates of the FET's and that, with it's span of voltages, that it would make the FET vary, isn't that? Because if I get more/less LFO signal (meaning level) on the gates, what does it mean, implies?

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A small detail is the LFO waveform is a "triangular" waveform plus a DC offset of about 4.5V.  That comes about because the circuit is single supply.   The DC offset does have an effect on the JFET biasing.   The bias trimpot has enough adjustment to factor in that fixed DC component.

It's a little confuse to me, the offset it's caused by what? It's the output of the op-amp? And how does the trimpot would adjust the factor? Is there any position where it would adjust less/not adjust?

All of these questions i'm bringing took in consideration that I already did some simulation on the P90 LFO but didn't manage to understand some parts/some responses of the circuit.

Rob Strand

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Yeah, I would have to try it in physical reality. So between TL072, LM393/339 and NE555 you would reccomend better the TL072 right?
The TL072 is fine there's plenty of opamp choices,  pretty much any opamp will work.


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What do you mean by voltage divider equation with R19 and R21? How do you come to that equation?
There's many ways to look at it, however looking it as a resistive mixer covers the Schmitt trigger and the combination of the bias Trimpot + LFO

https://www.allaboutcircuits.com/textbook/semiconductors/chpt-8/averager-summer-circuits/

Consider the case where you only have two voltage sources V1 and V2 and they feed their corresponding resistors R1 and R2.   The voltage at the output is a blend of the two input voltages.

Vout = (R2/(R1+R2)) V1  + (R1/(R1+R2)) V2

If you look at only one of the voltages, say V1, with no V2, you get a simple voltage divider equation,
Vout = (R2/(R1+R2)) V1

If you view circuit from V2's perspective, with no V1, you also get a voltage divider equation,

Vout = (R1/(R1+R2)) V2

The two input circuit is just the sum of both those separate results.  That works because of superposition theory.

You can also view this as a blender,

Vout = k * V1  + (1-k) V2;    where  k = R2/(R1 + R2)

k always between 0 and 1 depending on the resistor values.
k=1 select V1, k=0 select V2, k=1/2 is equal amounts of V1 and V2

For the schmitt trigger case, 
 V1 = the opamp output voltage, which is either 0V or 9V  ; actually more like 1V or 8V
 V2 = Vref = 4.7V
 R1 is R21 in the schematic
 R2 is  R19 in the schematic

From the two opamp voltage you calculate two voltages on U1b's +input   and they are the thresholds.

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Alright, that I can deal with. But we're talking about the C10, right?

Yes.

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And, I know you said to ignore C7 and R24, but how do they prevent those clicks? I can't see how..
It'a hard to expain.  When the opamp output tries to change state the cap C7 shifting the voltage.  Kind of like pulling  a piece of cheese on a string that a mouse is trying to get.    Have a play in spice with different C7 values.

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What do you actually mean? Because the 1M+trim
..
It's a little confuse to me, the offset it's

If  you look at this circuit as a resistive mixer, similar to the above,

Output = JFET gate voltage
V1 =  Bias Trimpot
R1 = 1M + adjustment trimpot
V2 = LFO out
R2 = 3M9 resistor.

The LFO output can be broken down in to and AC component and a DC component,

VLFO  = VLFO_AC + VLFO_DC

The gate voltage is then,

VGS = k * VBIAS + (1-k)*VLFO
          = k * VBIAS  + (1-k)*( VLFO_AC + VLFO_DC)
          =  {k* VBIAS + (1-k)*VLFO_DC} + { (1-k) VLFO_AC}
             
From the perspective of the JFET gate,

- the first {} is the true DC level and it depends on the bias trimpot adjustment and the also the DC level coming out of the LFO.

- the second part shows how much AC part of the LFO get through.  ie. the how the peak to peak at the LFO output
   gets reduced by a factor (1-k) before getting to the JFET gate.

   Since the 3M9 resistor is somewhat larger the the 1M you will find  k is about 0.8,  so 1-k is 0.2
   so the LFO swing at the gate is reduced somewhat compared to the swing the LFO output.
« Last Edit: September 17, 2020, 01:26:15 AM by Rob Strand »
Plopping around the pot since an early age.

savethewhales

.

Just something quick, is there anyway I can contact JC Maillet, the owner of the site you wrote me, personally? Because I looked at the explanation of his circuit of unmatched JFET's and I was completely buzzed about it. In a sense that it's very well done and he seems to know a looot about phasers, which could help me in this stage.

(I know he's a user here but I don't know how to reach personally).

savethewhales

So I have good news.

(The numbers of components R21, R19 etc come from the electrosmash schematic)
Before I start showing what I got in sims, let me say I did the math you instructed me to, and taking note that the op-amp would give me 0.1V to 8.9V in the output in the best case (and a 4.8 Zener), I got 3.663 V and 5.792 V as the thresholds in the Vout of the summer/blender, as the following image indicates (but not exact values of course, with a difference of 0.3V):



Now I can understand what you told me about the blender.

Following, I wanted to sim for my own FET's which are matched, and knowing that they are around -1,23 VGS-off, I knew I would want almost 1.23 Voltage span for my LFO (which I wasn't getting at all).
In that matter, I could calculate the Gate Voltages I would want: the less (in module) is 0V and the most is around -1.23 V.
For that to happen I need 4.8V and 3.57V coming from the LFO, respectively (taking account of 4.8V Zener).

For me to get to the part I want (outputing desired LFO voltage on the gates) I needed to tweak around the thresholds of the Schmitt Trigger and at the same time tweak with the Bias Voltage, so I did some simulation as will follow after the resume below:

                  R19      R21                      LFO voltage span                        Shape of the triangular wave
1-             150k    470k                          0.33 Vpp                                          very good
2-             470k    470k                          0.62 Vpp                                              good
3-             470k    150k                        Almost 1Vpp                                       not so good
4-             150k    800k                          0.25 Vpp                                           very good
5-             800k    150k                    1Vpp aproximmately                                 not good

sims (respective to the numbers above):











My conclusion is that I don't really need a perfect triangular wave so I've chosen 470k and 470k to start tweaking with. As I had better voltage span but not still the values I wanted I started tweaking with Bias and R20.
It wasn't very linear but with:

R19      R21         R20      VBias
470k    470k      2mega     4.0V

Which is this schematic:


I got what I wanted:


I'm only guessing the LFO on the P90 was just like that in the schematic because there were some poor jFET's with like -0.4 VGS-off that made it to the fabric. Other than that, if one doesn't change things to his/her behalf, it will get hard to get the full behaviour of the jFET's ohmic region.

Eb7+9


Just something quick...


a few key points
(... )

for decades now there's been this misleading (I'd say almost completely false) methodology perpetrated by guys with no real knowledge of circuit analysis and theory ... I've read many of the early sources and it's the same basic narrative over and over // often seemingly repeating manufacture application/marketinng notes that were written in a way intended not to reveal too much ... get my drift ?

phasor circuit design/behavior is a lot simpler than it's often made to appear, especially when the right design methodology is in place ... the key is to start out by separating the phasor system into its three constituent parts

---

If you *really* want to understand what's going on inside a phasor I would strongly recommend staying in the time domain at first - that's where the usual first mistake lies ... If you *really truly* want to understand what's going on inside a phasor get yourself a signal generator and dual-input scope and breadboard up a simple two-stager controlled from a dual 250k pot and "see for yourself" what happens to a sine wave against manual resistance variation ... then we'll have something beyond magical hand-waving to talk about // everything necessary for making the right conclusions will be there in front of you

next,
time to get past the resident fiasco that is jFET testing

recognize that I have strong views surrounding the unexplained magic that passes for a bone-fide test in this forum ... once you can get passed that idea read the Vishay paper on VCR use of jFET's and consider why the test that I and many other people recommend doing results in extracting two key (fixed) numbers for each device ...

here's a popular technique for estimating Vgs(off) that uses the high internal resistance of a DMM's volt meter to bias the jFET at ultra low-current levels:

https://viva-analog.com/jfet-characterization-technique-using-only-9v-battery-and-dmm/

simply put, any test that returns a single number must be wrong by virtue of the fact that jFET's have a two-dimensional error space // ... a conclusion that's beyond opinion or preference

furthermore, this two-part knowledge applies similarly to jFET's living inside active voltage gain stages (in particular, applying to recent questions about jFET linearity, input headroom, mu-stage transfer, etc ... all answered starting from this basic analysis) ...

there is no intelligent way around any of this

>>> for reference, these are same numbers (variables) that are listed in the Vishay paper, the same that are listed in textbook jFET equations, the same that are listed in data sheets ... strangely, this forum is the only place I know of where jFET's are not regarded in terms of their measured/estimated Vgs(off) and Idss values ... perhaps the reason for the recurring struggle we see here, in particular with jFET phasors

once you understand the Vischay "VCR" paper you'll understand that all jFET's are being controlled (or intended to) by a voltage that takes Vgs "somewhere" inside the Vgs(off)-to-0 range ... Vgs(off) being negative for n-channel devices ... how much of that somewhere being covered depends on the design ... for example, my MXR Phase90 LFO sim served to give specifics not seen elsewhere about that very key aspect ...

the Vishay paper makes it clear that we can talk in terms of a (normalized) control range percentage, all I'm doing in my Paradigm Shifter is using trim-pots to scale the control range on the device with the largest Vgs(off) value down to match subsequent Vgs(off) values that are not the same (and smaller) ... in the process matching the range percentage and relative idling location within each Vgs(off)-to-0 span ... in normalized terms, the same ...

no brainer \
*and fairly accurate as long as you use a meter with a high Zin like Rob pointed out last time

as for the control part of phasors I would encourage you to experiment and come up with your own way of interfacings things, as long as you understand the need to keep your gates in that Vgs ball-park now that you understand how all that works ... understand that when you do proper (high accuracy) jFET testing you end up with lot less false positives in the end ... which means going thru a truckload of devices just to get a good matched quad - hence the pull towards proportional scaling of the Vc control line

hope this helps

---

btw, here's a recent offshoot from my 2n5457 characterization work ...
providing an obvious solution to a basic re-design problem
https://viva-analog.com/viva-analog-1176x-jcmc2020/
Walter Becker's turf ...
DISCOVERY happens to prepared minds

savethewhales


a few key points
(... )

Wow thanks for answering.. I really apreciatte that. I don't even know how to start.

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If you *really truly* want to understand what's going on inside a phasor get yourself a signal generator and dual-input scope and breadboard up a simple two-stager controlled from a dual 250k pot and "see for yourself" what happens to a sine wave against manual resistance variation ...

I really really do, but actually don't have a scope here in my home, so I must be left with simulations on LTSpice...

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next,
time to get past the resident fiasco that is jFET testing

hope this helps

I actually read the whole paper and read all that you wrote. And it's really reasonable to measure the jFET's in two variables, so I've actually measured it in the way you recommended it (see in computer for better visualization of table):

Number of jFET                             VGS-off                            Idss(the negatives should be from polarity)
1                                                   1.304 V                         -2.29 mA
2                                                   1.283 V                         -2.36 mA
3                                                   1.306 V                         -2.22 mA
4                                                   1.276 V                         -2.33 mA

It's actually funny that this is my 3rd type of measurement of JFET's, and of course, the measurements are different from the last one, which are diff from the first, you know it..
Another thing is the seller wrote in a plastic: "2N5457 2.5 mA 1.2 V".. I have nothing to say about it.

It seems that the VGS-off values and Idss values are kinda close, which for me is actually sacred.

After reading the Vischay paper, I got to know a better way of not having distortion and having a more linear Rds curve, it's just that I don't look for anything too precise, in the sense that I am okay with having not so much headroom and maybe not so linear variation of Rds because I am just doing a project to college, I don't know how I would put those extra sources on the gates, and it's my first project of building electronics.. On top of that, I don't have very much time left.

That being said, all I want is t know what limits do I have to set my pedal for it to work fine and in the full range of the jFET's. I guess with the measurements above I could be fine.

The biggest reason why I wanted to reach you is because of the LFO, in the sense that it's very very sketchy (the original), and the explanations I see on the internet (apart from Rob's explanation) are incomplete and hard to explain in a presentation. I have simulations on the LFO done on a post of mine above, and will post more (regarding behaviour of C7 and R24).

Do you think the LFO circuit of the Phase 90 (with some tweaks, as I did) would be enough for me to oscillate from -0.2 VGS to -1.3/-1.4 VGS? Or it seems too hard to obtain given the limitatons of the LFO circuit?
Or do you have any other advice to give me regarding LFO, that could be better for me?
I already talked to lot of people, including my teacher and the options were letting it as it is, using NE555 or LM393. As I don't want tooo much precision (just something looked/felt like a triangle), I thought about staying with the TL072 and integrator.

Anyway after all this I would kindly ask you how can I reach you beyond this web site, maybe e-mail or whatever you would like, because I read your web-site post of Paradigm Shift and other things of yours (LFO sim and 2N5457 testing) and looks like you are experienced in the area/in phasors, and that's what I need the most to get things right now.

Thank you very much.

savethewhales

It'a hard to expain.  When the opamp output tries to change state the cap C7 shifting the voltage.  Kind of like pulling  a piece of cheese on a string that a mouse is trying to get.    Have a play in spice with different C7 values.

As usual, here are my simulations (only changing C7 and keeping things as they were for triangle between 3.6 and 4.8V).

Number of sim/image                          C7 Value                              Comment
              1                                           0.01uF                                no delay 
              2                                            0.1uF                            >1.2 seg delay
              3                                            0.5uF                 Even with 40 seg sim no change
              4                                             1nF                 Small delay (now smaller capacitor)
              5                                            0.1nF                   >1.5 seg Delay (smaller cap)











(Don't know how to put the images bigger).

As I can conclude, I couldn't seem to find anything reasonable to explain the bigger delays when the values of the cap differ too much from the original 0.01 uF positive or negatively..
But for experimentation, I could see that I would want to use the 0.01 uF cap, no more explanation possible. If someone knows the reasons behind these results please let me know. Thanks.

savethewhales

If  you look at this circuit as a resistive mixer, similar to the above... so the LFO swing at the gate is reduced somewhat compared to the swing the LFO output.

Perfect explanation. But there's always something more for me to search. In this case, where do you get the DC level coming out of the LFO? What sets it?

I ask this because I wanted to do the math, but without that I can't.

Although, without the LFO DC I could already calculate the percentage of AC passing through the gates, given the resistor network that I have on my schematic:



However I did math, with k=0.3 following your logic, and 1-k=0.7. With those values, I get AC of 4.27Vmax to 2.233Vmin, from which I calculated the diifference to know Vpp and it's 2.037, differently from my simulations which give me 4.62Vmax and 3.43Vmin, with a peak to peak voltage of 1.19 V.

Could I be doing something wrong?

Thanks, Fred

Rob Strand

Quote
As I can conclude, I couldn't seem to find anything reasonable to explain the bigger delays when the values of the cap differ too much from the original 0.01 uF positive or negatively..
But for experimentation, I could see that I would want to use the 0.01 uF cap, no more explanation possible. If someone knows the reasons behind these results please let me know. Thanks.
I recommend looking up how to set the initial conditions in spice.   You need to set IC=5V or IC=0.1V on C2.   The add UIC to the .TRAN analysis.

Start-up for oscillators in Spice is tricky.   They can do things that the real circuit doen't do.  Imagine inside the opamp there is transistors and JFETs.   In reality all those parts are slightly different.   However in Spice they are exact.   When the circuit powers up in spice it is "too symmetrical" there's is nothing to bias it to make it go one way or another.   It's like balancing a pin on he sharp point.  If the math is exact you can do it but in practice you cannot.     Also the electrical noise in each part of the the circuits different.   In spice you have rounding errors which can make the circuit behaviour changes and eventually start.


Quote
In this case, where do you get the DC level coming out of the LFO? What sets it?
The connection of R19 to Vref is the main that *sets* the DC level.  Apart from that, the opamp saturation voltages can affect the DC point but you have no control over these.   *if* you wanted to shift the DC point you can connect R19 to a different voltage.  Another way is to add a resistor from the opamp + input to +V or ground.

If you move the DC level away from Vcc/2 the timing capacitor will charge asymmetrically and that will mean the time to ramp-up with start to differ from the time to ramp down.  The square output will not be square.

A bigger problem is the DC output from the LFO depends on the battery state.  If the DC bias depends on the battery the bias adjustment becomes mis-adjusted when the battery goes flat.  The DC from the bias trimpot does not change with the battery state as much because the Zener helps regulate the voltage.    The MXR design makes R19 small so the LFO DC level is closer to Vref and less dependent on the battery.

Quote
However I did math, with k=0.3 following your logic, and 1-k=0.7. With those values, I get AC of 4.27Vmax to 2.233Vmin, from which I calculated the diifference to know Vpp and it's 2.037, differently from my simulations which give me 4.62Vmax and 3.43Vmin, with a peak to peak voltage of 1.19 V.

Could I be doing something wrong?
For 470k + 470k I get k = 0.5 and 1-k = 0.5.     VLFO = 6.3V and 2.85V
For 150k + 470k I get k =  0.24 and 1-k=0.76.  VLFO = 5.5V and 3.8V

Plopping around the pot since an early age.

savethewhales

Quote

I recommend looking up how to set the initial conditions in spice.   You need to set IC=5V or IC=0.1V on C2.   The add UIC to the .TRAN analysis.
...
 In spice you have rounding errors which can make the circuit behaviour changes and eventually start.



Tommorow as soon as I can I will do the simulations.
But, you're telling me these "delays" are non-reality? So what does the C7 affect then?

Quote

The connection of R19 to Vref is the main that *sets* the DC level... The MXR design makes R19 small so the LFO DC level is closer to Vref and less dependent on the battery.


So how do I know that R19 is bringing DC to the circuit? Because of the current that comes from the 1Mresistor+Trimpot that enters the LFO? Because I'm not seeing any other way around...

One important thing is the zener then, for setting the DC more stable... Ok.
I actually will use a switcher between 9V source and a battery, so there shouldn't be a big problem.

Quote
For 470k + 470k I get k = 0.5 and 1-k = 0.5.     VLFO = 6.3V and 2.85V
For 150k + 470k I get k =  0.24 and 1-k=0.76.  VLFO = 5.5V and 3.8V

Rob, I was actually doing the math for the input of the Gate Voltages (which are different from the output of the LFO) with these maths that you quoted. The maths that you did I also did somewhat above that, with similar, if not the same results.
But thanks anyway!

Rob Strand

Quote
But, you're telling me these "delays" are non-reality? So what does the C7 affect then?
The delays you are see are not realistic, they occur because the mathematical exactness of spice make it difficult for the oscillator to start.   There are delays associated with C7.  They occur on a small time scale 150k * 10nF = 150uS.  That enough to slow down the edges of the opamp.   If you put in 1uF the delays are 150k * 1uF = 150mS.   That will start to change the frequency of the LFO a bit.

Quote
So how do I know that R19 is bringing DC to the circuit? Because of the current that comes from the 1Mresistor+Trimpot that enters the LFO? Because I'm not seeing any other way around...

Current doesn't come from R19.  R19 *determines* the voltages on the timing cap.  Current can come from the opamp output via R2 on your schematic (R36 on electrosmash link).

As an experiment try connecting a resistor (say the same size as R2 on your schematic) from the timing cap to ground and then to Vcc.   Notice how the cap voltage swings to the same peak voltages but on and off timing ratios are changed.

The DC offset from the LFO can be a little confusing because it depends on how you look at it:

If the average level at the output of the oscillator is Vref, you can consider the DC level Vref.  Since the JFET drain source is at VREF the LFO DC level has little effect.   In the real circuit it has a small effect because the oscillator DC level isn't quite at Vref.

The other way to look at the LFO is to think of the minimum voltage as a DC offset.    The reason you would think like this is because the most critical part of the circuit is the JFET voltage when is gets close to Vgs_off.   This is when the JFET resistance is the highest.  That occurs when the LFO is the lowest output.   If the minimum voltage changes because you have played with the part values then  you would need to adjust the bias trim pot to compensate.

It might be a little confusing.   The whole reason you need matched JFETs is so the JFET resistance tracks when the JFET voltage is at the lowest point.    In this region small changes in the gate voltage produce large changes in the JFET resistance.

« Last Edit: September 20, 2020, 07:04:11 PM by Rob Strand »
Plopping around the pot since an early age.

savethewhales

Tommorow as soon as I can I will do the simulations.


So I did it. Thanks to you Rob, for advising about the initial conditions.
The sims were with this circuit:



First, messing with C7.

          C7              Comment
1-      0.01uF          very good
2-      0.1 uF           Less sharp
3-      0.5 uF         Way less Sharp
4-      1 nF              very good
5-      0.1 nF           very good
6-      0.01 nF         very good

(in order):








Now sim messing with R24.

             R24              Comment
1-      150k               very good
2-      50k                 very good
3-      10k                 very good
4-      700k               Less Sharp
5-      1.2 mega         Less Sharp
6-      3.3 mega         Less Sharp
7-      10 mega        way less sharp

(in order):









I guess I can conclude that the resistor with the capacitor form a filter for the output of the schmitt trigger in a sense that they reflect the sharpness of the transitions on the op-amp. Am I right? And is it a simple RC filter, or smth else?

Thanks