Author Topic: Help with the simulation of Phase 90 on LTSpice!!! JFET's giving 0.3 Volt sweep  (Read 11042 times)

Rob Strand

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*EDIT*: Managed to get nice and clean waves. The problem was the amplitude of minus than 100mVp, it gave me too much noise.. (the following has 1V peak on input):
OK no problem.    Grounding the metal plate on the breadboard can help reduce noise.   Also use shielded cables, and keep the cables short.   It's good to know how to reduce external noise because sometimes you don't have the luxury to increase the input level.

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All of this was very important for me to do because I could see that the results of rds were not even close to what I measured (after all the methods used I got around 320 ohms), what means that only by doing this type of test was I able to see how my recent bought FET's responded.

For you case of 47k in parallel with 24k, I get 213Hz for the notch.   So all resistor test looks OK.

For the JFETs,  I'm not sure what is happen here either.

When you test with JFETs the signal level can affect the results,   especially if you are driving more than about 500mV peak.   The JFETs are non-linear.    (I can't say this is the cause in your case.)

For the low resistance test, if the way to set-up the trimpot shorts the gate and source then that test should be a good indication of the JFET resistance.

For the Vgs = -1.3V test.   This region is very sensitive to the Vgs voltage.   I wouldn't worry about the results.

What you should do is a test with Vgs set to around -Vp/2.

The other thing is to verify the JFET resistance with a divider circuit for the Vgs=0 and Vgs = -Vp/2 cases.

It's worthwhile using an oscillator an oscilloscope to find where the notches are manually.    Try different signal level to see what affect the signal level has on the notch.    That gives you a good idea where is should be.  If the Audio precision test unit gives different results the test signal level could  be affecting the results.   Signal distortion, caused by driving the JFETs too hard, can sometimes cause test systems to produce incorrect results.

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I didn't even had much time from the moment I made the circuit work, so I couldn't test exactly if the vpinch-off of those FET's was really -1.3V, or if it was different too (but making the calculations it seemed correct).
Probably worthwhile since it can affect the results.

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Now besides all of that, and after seeing the images, I wanted to know what is that attentuation that I have on the low frequencies (-6dB on the 20Hz)? I made calculations to not lose audio frequencies, and that count

The problem is probably caused by the 10nF output capacitor.   I'm seeing roughly -3dB at 60Hz, and that means you only need about 270k load.    For a test set-up you want to make sure the load can't affect the results.    Use a big one cap for testing like 1uF.

One other thing I noticed.   You always got 5dB and not 6dB for the maximum gain.     The 33k and 470k is forming a divider which loses -0.6dB.    If you dropped the 33k to 4.7k it would reduce the loss.
Plopping around the pot since an early age.

savethewhales

OK no problem...       If you dropped the 33k to 4.7k it would reduce the loss.

One thing good about all this is (just like some one said on this forum,), is that you always make me look for more, and that is beyond good..

Some points before I do the testings today:

Input never passed 100mV peak because of the FET's limit.

I tried to see the extremes of the FET's to see how they responded and the maxium/minimum resistamces.
Anyway in the 0 VGS, I put thesame voltage on the Gate and the Source, namely 4.8 V.

I will do the jFET test on -Vp/2 to see how it reacts.

One thing: how can I know where the notches are manually? By changing the frequency on the input sine right?

Will also check for the gain of circ and the cutoff frequencies of the high passes.

Rob Strand

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Input never passed 100mV peak because of the FET's limit.
100mV pk is very conservative.     The error due to non-linearity rises slowly with the peak.  I wouldn't be too worried about 200mV pk if you had to go that high.  However above 500mV pk you would expect some effect on the measurements (maybe 10%).

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I tried to see the extremes of the FET's to see how they responded and the maxium/minimum resistamces.
Anyway in the 0 VGS, I put thesame voltage on the Gate and the Source, namely 4.8 V.
I will do the jFET test on -Vp/2 to see how it reacts.
The main thing is to try to work out why you measurements are off from the theory.   If you can build a simple divider and measure rds for those Vgs values it should give you an idea what to expect when you put the same JFET with the same voltage into the phaser circuit.

Something weird would be going in if the divider looked like one rds value and the divider looked like another when Vgs was set to the same value.

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One thing: how can I know where the notches are manually? By changing the frequency on the input sine right?
Yes.  Set the level and look at the oscilloscope for the minimum.

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Will also check for the gain of circ and the cutoff frequencies of the high passes.
If you change the output cap I'm sure you will be OK.   Of course you can try to match-up the -3dB point with theory based on the cap value and the load resistance.
Plopping around the pot since an early age.

savethewhales


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100mV pk is very conservative.     The error due to non-linearity rises slowly with the peak.  I wouldn't be too worried about 200mV pk if you had to go that high.  However above 500mV pk you would expect some effect on the measurements (maybe 10%).

OK!

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The main thing is to try to work out why you measurements are off from the theory.   If you can build a simple divider and measure rds for those Vgs values it should give you an idea what to expect when you put the same JFET with the same voltage into the phaser circuit.

Something weird would be going in if the divider looked like one rds value and the divider looked like another when Vgs was set to the same value.

I am testing right now with a potentiometer as a voltage divider. On maximum (4.8V) is giving me 12.75kHz notch now (?) and minimum is giving me 157 Hz. This is giving me rdson=265.6 ohm for the maximum. Not bad.

Doing a very slow turn I found out the Vpinch off that I calculated is almost right. I am getting -1.33 Volt.

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If you change the output cap I'm sure you will be OK.   Of course you can try to match-up the -3dB point with theory based on the cap value and the load resistance.

Worked! Thank you and PRR!

savethewhales

First things first:

By doing a simulation on Matlab, I could see that the maximum frequency that a 1 stage phaser needs to have, for me, is 8261.7 Hz (417 ohm on rds, which gives me more than 20kHz when I use 2 stages). So, that's what I searched for with the audio precision unit and messing with a potentiometer to the gates of the FET's.

I found out that with the 2 first testing FET's I couldn't pass the 4.27Volt mark and with the 2 last testing FET's I couldn't pass the 4.2 Volt mark.

After that, I tested the 2x pair of FET's to their maximum and miinimum values of equivalent resistance.

(this site doesn't accept the type of file that the APX exported)

With 0 V on the gate :
- Pair 1 of FET's:
160 Hz notch

- Pair 2 of FET's:
160 Hz notch

With 4.8 V on the gate :
- Pair 1 of FET's:
21,625khz notch

- Pair 2 of FET's:
21 khz notch

This means that the minimum resistance lies around 175 ohm if I'm not mistaken, and that doesn't match with my early measurements. No problem because I wouldn't even need to use less then 417 ohm rds.

Then, I tested to see in what EXACT voltage on the gate would the FIRST change on the first notch be:
- Pair 1 of FET's:
3.41 Volt

- Pair 2 of FET's:
3.47 V

With that I conclude that my early measurements of VGS were somewhat close (I measured -1.3 V generally, and here I got around -1.33 to -1.39 V).

Also, I tested both pair of FET''s and I slowly increased the voltage on the input to see how they reacted: I reached 1Vpeak without any change on the waveform/anything suspicious. Anyway I decided to stop there.

 

savethewhales

I managed to confirm the limits which I can use with my LFO, which are 3.4 to 4.2 Volt on the Gates.
That gives me 0.8 Volt range on the LFO. 

Realizing that the less the range, the worst is the "triangular wave", in general.. Can someone explain to me why this happens, and how can I fix it?

Before I had this:



But by changing the components to get less range than what I had, what I ended up is with this:



Now what happens is that this is the final LFO circuit I designed:



Where R1 is a 470k pot, R5 is also a pot, and C1 is 100uF (this one to me is smelling like trouble, but it's what I found out to be the best).
In practice I get around 0.3 to 8 Hz of LFO (while the higher frequency gives me a wave that is very distorted, just like shown above), while on theory the results give a bit different taste.

And actually the DC level is not yet set right (maybe it is, but I haven't tested the DC level on the osiloscope yet).

Rob Strand

The problem is the square wave (on the input) is feeding through the integrator.  It's like the two parts of the triangle separate.

Many possible causes, you would need to probe the circuit to find something,
- Vref is shifting when the Schmitt-trigger changes states
- Could be related to the 100uF cap.
   Are you using a non-polar cap or an electrolytic?
- High impedance in the ground wires or bad ground connections.


See how two electrolytics are placed back to back to emulate (C27 & C28)   non-polar cap (of half the value),
https://www.hobby-hour.com/electronics/s/schematics/boss-bf2-flanger-schematic.gif
« Last Edit: October 05, 2020, 07:27:25 PM by Rob Strand »
Plopping around the pot since an early age.

savethewhales

The problem is the square wave (on the input) is feeding through the integrator.  It's like the two parts of the triangle separate.

exactly! But like, how can I avoid it...

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Many possible causes, you would need to probe the circuit to find something,
- Vref is shifting when the Schmitt-trigger changes states
- Could be related to the 100uF cap.
   Are you using a non-polar cap or an electrolytic?
- High impedance in the ground wires or bad ground connections.

When I can I will check it (but how can I probe if it changes all the time?).

I'm curious to see how vref behaves with this.. It's very possible that it's shifting.

The 100 uF cap was put there after me getting the image I put above, and it's electrolytic (the minus is on the output of the first op amp)

About the ground wires, how can I make the impedances smaller then?

And for the ground, I checked it like 20 times (because last time I had problems with it) and nothing...
[/quote]

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See how two electrolytics are placed back to back to emulate (C27 & C28)   non-polar cap (of half the value),
https://www.hobby-hour.com/electronics/s/schematics/boss-bf2-flanger-schematic.gif

Pretty interesting! But why not use only one non-polar cap? hahah

Rob Strand

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exactly! But like, how can I avoid it...
It's more a case of finding the cause.


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When I can I will check it (but how can I probe if it changes all the time?).
Use the oscilloscope.  Find a place in the circuit which shows a small square-wave at the LFO frequency   Start investing the cause.

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I'm curious to see how vref behaves with this.. It's very possible that it's shifting.
At this point it is quite possible.  The power rail fluctuating can also cause it (the zener should remove most of it).

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The 100 uF cap was put there after me getting the image I put above, and it's electrolytic (the minus is on the output of the first op amp)
Ok an electrolytic probably isn't the right thing for the job there.  It could be causing the problem.

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About the ground wires, how can I make the impedances smaller then?

And for the ground, I checked it like 20 times (because last time I had problems with it) and nothing...

Good chance it's not the problem then.

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Pretty interesting! But why not use only one non-polar cap? hahah
When that circuit came out large bipolars weren't so popular so the designers chose to make their own.

It's probably worth your while changing the cap from a single electrolytic to a non-polar, or doing the two cap thing if you don't have the bipolar caps on hand.
 
Plopping around the pot since an early age.

savethewhales



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Use the oscilloscope.  Find a place in the circuit which shows a small square-wave at the LFO frequency   Start investing the cause.
Nice.. Will do it when I am able to use an oscilloscope again.

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At this point it is quite possible.  The power rail fluctuating can also cause it (the zener should remove most of it).

What you mean? All I'm thinking is the reverse diode in the power supply section which I haven't put there yet.. Something to do with it also? Or the zener does the job?

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Ok an electrolytic probably isn't the right thing for the job there.  It could be causing the problem.
Ok. It's what I had unfortunately..

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When that circuit came out large bipolars weren't so popular so the designers chose to make their own.

It's probably worth your while changing the cap from a single electrolytic to a non-polar, or doing the two cap thing if you don't have the bipolar caps on hand.

Ok. I'll try to make the testing on the oscilloscope with a non-polar cap (or two equal in reverse series).
Also, could I make a non-polar one by reverse paralleling two of them? It seems right to me also..

savethewhales

I'm seeing now that when I'm messing with "my" depth pot, it is also messing with the LFO frequency! What can I do about that? Someone please?

Rob Strand

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What you mean? All I'm thinking is the reverse diode in the power supply section which I haven't put there yet.. Something to do with it also? Or the zener does the job?
You would expect the zener to do the job.   However if something is wrong, then problems can still show up.  What are you powering the pedal from?  Look at the power rails with the oscilloscope.

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Also, could I make a non-polar one by reverse paralleling two of them? It seems right to me also..
Electrolytic caps can conduct when reverse biased so when you put them in "reverse parallel"  they will conduct in both directions.  So "reverse parallel" is never good.     In simple terms think of a electrolytic cap having a diode connected in parallel with the cap.  In the correct polarity the diode has no effect but the in reverse polarity the diode conducts and it no longer behaves like a cap.    Electrolytics have a complicated internal structure, not just two simple plates,  a reverse voltage cause the insulating oxide layer to be removed and it starts to conduct.

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I'm seeing now that when I'm messing with "my" depth pot, it is also messing with the LFO frequency! What can I do about that? Someone please?
Can you post a schematic?

The depth affecting the LFO and the square-wave feed-through might be related.
Plopping around the pot since an early age.

savethewhales

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You would expect the zener to do the job.   However if something is wrong, then problems can still show up.  What are you powering the pedal from?  Look at the power rails with the oscilloscope.

Power supply of 9V (not battery yet).


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Electrolytic caps can conduct when reverse biased so when you put them in "reverse parallel"  they will conduct in both directions... a reverse voltage cause the insulating oxide layer to be removed and it starts to conduct.

Hmm alright!

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Can you post a schematic?

The depth affecting the LFO and the square-wave feed-through might be related.



Here 'Tis. I already understood that the depth pot cannot be placed there because it affects the duty cycle, which in connection with the integration time will not give me what I want..

However, I've been searching on the net, and I find that it's possible to do what I want, which is amplifying the triangle (or attenuating it), and being able to change the DC offset of it(for the gates of the jFET's, which need to have a certain voltage).

This site mentions one way to do it:

https://electronics.stackexchange.com/questions/162886/non-inverting-op-amp-with-dc-offset

Does it make any sense?


Rob Strand

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Here 'Tis. I already understood that the depth pot cannot be placed there because it affects the duty cycle, which in connection with the integration time will not give me what I want..
More the problem is the depth affect the frequency.    When you reduce the cap reaches the Schmitt-trigger level earlier and the frequency goes up.


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However, I've been searching on the net, and I find that it's possible to do what I want, which is amplifying the triangle (or attenuating it), and being able to change the DC offset of it(for the gates of the jFET's, which need to have a certain voltage).

This site mentions one way to do it:

https://electronics.stackexchange.com/questions/162886/non-inverting-op-amp-with-dc-offset

Does it make any sense?

It's adding an extra stage you don't need.    The AC coupled one is going cause unnecessary problems since you lose all you DC levels (not to mention the use of 100R resistors couldn't be worse from a design perspective!)

The depth on these is far more economical,
https://www.hobby-hour.com/electronics/s/schematics/boss-bf2-flanger-schematic.gif
https://www.hobby-hour.com/electronics/s/schematics/boss-ce2-chorus-schematic.png
Plopping around the pot since an early age.

savethewhales


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More the problem is the depth affect the frequency.    When you reduce the cap reaches the Schmitt-trigger level earlier and the frequency goes up.
Exactly.. Not what I wanted. I'd like to have a fixed frequency and then change the amplitude of the wave (but maintain the DC offset)

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It's adding an extra stage you don't need.    The AC coupled one is going cause unnecessary problems since you lose all you DC levels (not to mention the use of 100R resistors couldn't be worse from a design perspective!)

The depth on these is far more economical,
https://www.hobby-hour.com/electronics/s/schematics/boss-bf2-flanger-schematic.gif
https://www.hobby-hour.com/electronics/s/schematics/boss-ce2-chorus-schematic.png

Ok.. It's just that I've been searching about shifting the DC levels but cannot find something that's too different than this:



Could there be any better way?

As for the circuits you recommended, I'm kind of a dummy to understand these big ones. But I'll try:

For the Boss BF2, the depth is simply a divider of the R48?? I mean, I don't understand what Q8 does there..

For the CE2, the depth is a divider with the R35? And it seems like it''s feeding back to the LFO (maybe the BF2 does too).
I don't seem to understand easily those depth pot's.. If it's just a divider, I've tried to do it but what it does is it actually shifts my DC level also, which is something I didn't want.

savethewhales

Well, thanks to your help with those schematics, I've desiigned a voltage divider with reference to the virtual ground to change amplitude and a voltage divider with reerence to ground to change the DC Offset!

And it works! Do you think it's a good idea?

EDIT: it doesn't, because the voltage divider with reference to ground changes the amplitude of the wave... Does anybody know how to change the DC offset?
« Last Edit: October 07, 2020, 12:33:21 PM by savethewhales »

savethewhales

Hi everyone.

I'm happy to say that I managed to do a LFO as I wanted.
The circuit is the following:



A quick explanation: down below is the "whole" power supply part, and up is the voltage supply from battery/power supply, which is +9V/0V.

In the middle is the whole LFO.

To the output of U8 where it says "Vastable" is the output of the astable multivibrator. After that there's a voltage divider to set the maximum voltage range preferred by me (the output is by the name of VFullRange). Then there is the potentiometer of depth which changes the voltage range from the maximum value to a minimum value.

And at the end, there's the part where I change the DC Offset to center the triangle where I want, namely the 3.8V (which by the divider made by R12 and R13 - a trimmer - should be 105.5kohm on the R13).
It all looks good and I think I managed to isolate the input of the last op-amp with the previous DC values.

Now the only thing which bugs me is this response:




Things were doing alright, and this "delay" started after I started messing with capacitor values. Now it's nearly 100 seconds for it to get stable at 3.8V center...
I'm gessing (and hoping) that this is because of the limitations of the capacitor times that Spice takes into account.. And I'm praying that this doesn't happen in real life.. Because everything else is well.

Does anybody know this?

Thanks in advance!

Rob Strand

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For the Boss BF2, the depth is simply a divider of the R48?? I mean, I don't understand what Q8 does there..

For the CE2, the depth is a divider with the R35? And it seems like it''s feeding back to the LFO (maybe the BF2 does too).
I don't seem to understand easily those depth pot's.. If it's just a divider, I've tried to do it but what it does is it actually shifts my DC level also, which is something I didn't want.
You don't need to worry about R48 and R35 they belong to the next part of the circuit  If your circuit has such a resistor then leave it it..  The LFO + depth stops at the depth pot wiper.

The difference between the BF2 and the CE2 is the circuit around Q8.    The Q8 circuit set the DC level when the Depth pot is minimum.    The Manual control lets you set that DC offset.     The main thing to realize when the Depth is set at minimum you want want to think about what DC voltage you want.  Different DC voltages will also change how the pedal sounds when the Depth pot at other setting, for example mid-way.


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And at the end, there's the part where I change the DC Offset to center the triangle where I want, namely the 3.8V (which by the divider made by R12 and R13 - a trimmer - should be 105.5kohm on the R13).
It all looks good and I think I managed to isolate the input of the last op-amp with the previous DC values.

Now the only thing which bugs me is this response:


The circuit is AC coupled.   You don't *have to* AC couple the circuit.   To AC couple the time-constant of the AC coupling network needs to be long in order to not filter the LFO.     The side effect of that is a very long start-up transient.   The best way to stop that is to DC couple.
Plopping around the pot since an early age.

savethewhales


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You don't need to worry about R48 and R35 they belong to the next part of the circuit  If your circuit has such a resistor then leave it it..  The LFO + depth stops at the depth pot wiper.

Yes! My circuit has that of the depth with only a pot really..

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The difference between the BF2 and the CE2 is the circuit around Q8.    The Q8 circuit set the DC level when the Depth pot is minimum.   
Why would I want a DC level when the depth pot is at minimum?
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The Manual control lets you set that DC offset.

How? That actually interests me, cause that's what im kinda searching..
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   The main thing to realize when the Depth is set at minimum you want want to think about what DC voltage you want.

Ok. But that's because in that schematic, the LFO changes its center voltage?
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  Different DC voltages will also change how the pedal sounds when the Depth pot at other setting, for example mid-way.
For sure, cause the upper side of the LFO wave will be even upper or the lower side even lower.

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The circuit is AC coupled.   You don't *have to* AC couple the circuit.   To AC couple the time-constant of the AC coupling network needs to be long in order to not filter the LFO.     The side effect of that is a very long start-up transient.   The best way to stop that is to DC couple.

Ok, this is where I get confused.. All I want is to set the DC level (which was around 4.8V) to center the triangle at 3.8 V.. How can I do it? Or I change the time constant in the circuit I done, or I do a DC couple? Is that it?

savethewhales

I'm just asking about those things because in the morning (which is 10 hours from now ) I'll be able to test it in oscilloscope, etc.