Thanks! Well, we always want the lowest possible Vgsoff at a given Idss or the highest possible Idss at a given Vgsoff, don't we?

Well at least for the buffer. For the common-source type amp I'd have to think about it.

But within any given type of JFET, Vgsoff and Idss have a fixed correlation. Correct me if I'm wrong. So my question was more, if I have to choose between lower Vgsoff or higher Idss, which do I prefer for a buffer?

Based on the previous argument we can use the output resistance ro as a guide.

Since,

ro = (1/2) VP/ sqrt(ID IDSS)

If we say for a given model of FET the parameters scale with 'a' as

VP = kV * a^2 and IDSS = kI * a^3

where, kV, kI are constants.

then

ro = (1/2) kV a^2 / sqrt(ID kI) / sqrt(a^3)

= constant * (1/sqrt(ID)) * sqrt(a)

so for low ro we would choose a lower 'a' and that means the lower VP and IDSS.

This is a first order approximation. IIRC the scaling of VP and IDSS doesn't quite follow powers of 'a' I've indicated for VP and IDSS, especially when VP & IDSS are at one of the extremes (can't remember which end

). The square root varies slowly so the gains for smaller VP's are small over other VP's. Also, we don't want to choose an IDSS so low that we can't get full output into the load + RS - as per design constraints at the end of the previous post.

FWIW, it would be worth verifying this conclusion.

[EDIT: In spice, I scaled three JFETs according to 'a' and the lowest 'a' had the highest gain and lowest distortion.

So, assuming the scaling powers are correct, the conclusion holds that using the smallest VP (and IDSS) is best. ]