Designing a channel footswitch for the Mesa Boogie Mark V (logic switching)

[omnia:arts]

Elliot Sounds has some great logic switching circuits using CD4043 (and other chips) and/or 555's with relays. I breadboarded them for a 3 channel amp I built that I want to control via footpedal momentary switches.
Like someone else mentioned an Arduino Nano is also quite capable of performing the same thing but with a bit less wiring. Both included LED indication.

[ianmgull]

Quick update, it works!!!

I'm going to put together a PCB layout for anyone interested in downsizing the massive factory foot switch. One point to make: for reasons beyond me, pinouts for two of the three IC's are mirrored. Make sure to double check pinouts if you use the schematic from earlier in this thread.

[ElectricDruid]

Nice work, ianmgull. Isn't it great when it works?!? 

> what's going on inside the amp

Look what is there. A 10K and 1.5k/3.3k/5.6k. Just like that we have:
10K:1.5K  0.65V
10K:3.3K  1.240V
10K:5.6k  1.795V
Thresholds of 0.92V and 1.5V would sort the three values. A resistor-string, half a LM324, and a couple diodes.

Is it that simple, Paul? Won't the other two non-grounded resistors be connected to 5V, and therefore in parallel with the 10K? So the three cases would be:

(10K||5K6||3K3) : 1K5
(10K||5K6||1K5) : 3K3
(10K||3K3||1K5) : 5K6

(can't be bothered to work those out, sorry)
Still, it's the same idea - create some distinct voltages to tell the amp what to do. It's a resistor DAC, of sorts.

The circuit is interesting, and wastes at least half a chip in every IC they used! There's the dual 4-input NAND, only one of the two used. All that does is generate a clock pulse when any button is pressed, and not generate one if further buttons are pressed while one is held down.
Then there's the octal D flip flop, of which they've used only three. That stores the state, and it's inverting, so when a switch goes low, the flip-flop outputs a high. Those three flip-flop outputs switch on one of the LEDs, and also drive the hex inverter chip (only half used too) which flips high outputs into low outputs so only a single resistor is grounded at any one time. This is the 3-bit DAC which provides the final voltage output to the amp.

[ianmgull]

Nice work, ianmgull. Isn't it great when it works?!? 

It's so rare that things work on the first try that I just have to bask in this feeling. 

The circuit is interesting, and wastes at least half a chip in every IC they used!

I noticed the same thing. Since the goal here is making a compact foot switch, I'm tempted to see if I can find the same logic circuits in smaller dip packages. I think it's just one 4 input NAND, three G flip flops, and three inverting buffers.

I should probably decide what size enclosure I'm going to use first.

[ianmgull]

Quick question for anyone that might know:

Each of the three IC's has a .1uf cap between its +5v supply and Ground. What does that do, and why three identical caps instead of one larger cap?

[MikeA]

Each of the three IC's has a .1uf cap between its +5v supply and Ground. What does that do, and why three identical caps instead of one larger cap?

The IC data sheets recommend this, a 100nF cap to ground as close as possible to the IC on the power rails, to reduce incoming noise from less-than-perfect power supplies.

[PRR]

> reduce incoming noise from less-than-perfect power supplies.

And also to locally source the transient switching current spikes. This was essential on TTL, and became general habit.

[ElectricDruid]

> reduce incoming noise from less-than-perfect power supplies.

And also to locally source the transient switching current spikes. This was essential on TTL, and became general habit.

+1 what Paul said. You'll see 100nF caps like this next to every chip on old logic boards. They provide a little reservoir of power for the chip which stops it from hitting the power supply when it switches. They need to be as close as possible to the chip, which is why there can't be just one big cap doing the same job.

[marcelomd]

Not only digital, but analog chips benefit from having a nearby capacitor, usually 100nF, on the power supply pins.

Single supply opamps use one. With dual supplies I've seen one (between +v and -v), two (between each v and gnd) and recently a friend recommended three (which seemed too much, honestly)

[ianmgull]

Well folks, I'm back at it...

I've decided that it would be really swell if I was able to design a 2 button version (which still operates all three channels mind you) instead of a gluttonous 3 button version. This involves designing a finite state machine, which being an analog guy, fills me with terror.

Somehow, I'm most of the way there. I'm having a tiny problem debugging the circuit though, so if there are any digital logic gurus around, I'd appreciate your input (tehe).

I'm attempting to design a finite state machine and am simulating it on Circuit Verse (a digital logic simulator). The circuit behaves as expected until I feed the current state back into the input of the machine. When I do this, I get the following error:

"Simulation stack limit exceeded. May be due to cyclic paths or contention".

I'm not sure if this is a peculiarity of the simulation, or an error in my design. Here is the over-all design:

There are three states and two momentary switches used to move between states. The flow chart is below:

https://imgur.com/a/f2yX1DX

From this chart I created the following truth table, where A and B represent the first and second switch being pushed respectively, S0 and S1 represent the current state, and S0+ and S1+ represent the future state (given the current state and a combination of button pushes):

A | B | S0 | S1 | S0+ | S1+
---|---|----|----|----|----
0 | 1 | 1 | 1 | 0 | 1
0 | 1 | 0 | 1 | 1 | 1
0 | 1 | 1 | 0 | 0 | 1
1 | 0 | 1 | 1 | 1 | 0
1 | 0 | 0 | 1 | 1 | 0
1 | 0 | 1 | 0 | 1 | 1


From the truth table, I arrived at the following Boolean expressions for S0+ and S1+:

S0+: (A' B S0' S1) + (A B' S0) + (A B' S1)

S1+: (A' B S0) + (A' B S1) + (A B' S0 S1')

I designed logic gates around these statements using AND and OR gates, and fed the output of these (which represents the current state) into a pair of D-Latches. This is illustrated below:

https://imgur.com/a/SGOwNfn

The two circles in the top left are the two momentary switches. The two toggles to the right of those are used to represent the current state.

In a properly designed state machine, the value of the current state is fed back into the input from the output of each D-Latch. In my case however, that is when my circuit produces the aforementioned error. As a proxy, I've added the toggle switches to input the current state. In this configuration, it works as expected. However whenever I remove the toggle switches and feed the current state back in, I receive the error.

In case it makes a difference, the clock input of the D-Latches are being triggered by the XOR gate which detects when one of the two switches is pressed. I suspect the problem might be related to this but haven't narrowed it down.

[ianmgull]

For anyone wondering, the problem was that I was using a D-latch (which I believe was triggering on the rising edge of the "clock". I was able to get the circuit to work by using a T-Flip Flop (which I think is triggering on the falling edge like one would expect).