Author Topic: Biasing jfet by Rdrain with fixed Rsource  (Read 1345 times)

hans h

Re: Biasing jfet by Rdrain with fixed Rsource
« Reply #20 on: January 22, 2021, 04:43:01 AM »
@GibsonGM: I do not have a scope. What I do have is somewhat similar: play guitar into looper => looper into pedal. Use a guitar cable with cap on hot side, ground to pedal enclosure. Then into amp => I can touch the circuit at various points to see how it sounds. I use that for debugging as well. That way I can also hear what each consecutive transistor is doing, but I need some more experience in the "tuning by ear" department.

hans h

Re: Biasing jfet by Rdrain with fixed Rsource
« Reply #21 on: January 22, 2021, 05:09:47 AM »
Is this for an "amplifier"? IMHO (I am aware of other opinions) an amplifier's plate/collector/drain resistor should be proportioned to the LOAD. Often 1/2 to 1/5th the load impedance. Then fiddle the cathode/source bias to set the plate/drain "correctly". Correct may be very low for maximum voltage gain or midway between Vs and Vdd for large signal performance.

I saw a similar answer of you in another thread, but do not know how to go about computing the load impedance.
This is for a stompbox based on a tube amplifier schematic. The 7htheaven is based on a bogner and after this I'd like to fiddle around with one of the small supro schematics. There will be some voltage gain, mainly to induce clipping in next stages. The whole impedance thing often has me puzzled. For example: input impedance of a stompbox depends on inp. impedance of the first transistor, AND on the value of resistor connected in series with input, AND on the value of resistor connected from input to ground (also anti-popping resisistor). Quite complex to me. Since I'm talking stompox, there is no speaker driving involved, just Q1 driving Q2 etc, and finally Q4/Q5 driving whatever comes next. So how to compute input impedance or load impedance of each stage?

Thanks in advance, Hans

GibsonGM

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Re: Biasing jfet by Rdrain with fixed Rsource
« Reply #22 on: January 22, 2021, 06:14:52 AM »
Hi Hans,

Yes, using a debugging audio probe, you can listen to each stage as you go.  Looper would probably work just fine; I play a little as I go, just the guitar in since that is what I'll be using (old school).   I detach the coupling cap from anything following it and listen there; it may not matter whether the FET is loaded or not tho.  You'll find a range of reasonable sound on your trim pot that is quite narrow, in my experience.  You could start with a 10k or 20k pot (depending on your FET), tune until you get sound...measure the pot out of circuit, replace with a smaller pot and fixed resistance and use the smaller pot to 'tune it' if necessary.  Sometimes the 10k pot is enough.     I find that if you do it stage by stage with no pre- or post circuitry connected (so, one at a time as you build), if you shoot for 'clean and bright' tone, once they're all together they will clip nicely and not be buzzy or shrill.   Once several stages are together, it might be worth listening to them in sequence again to see what's going on.  Just how I do it (I'm sure many do this).  Interestingly I did find that 1/2 supply is almost never where you end up...I've also found when I do this 'manually', and THEN look on a scope, I've never ended up with a clean signal - what is musically pleasing is always a little offset (1kHz signal for scope work).     

It's very nice to know how FETs work and how to calculate impedances and so on - I do that for tube design.  Others have done enough design with FET boosts and preamps, I just copy what they've done, ha ha.  Then tailor them for different FETs I might have as I said above.   They were already paid to do all that hard work  :)
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hans h

Re: Biasing jfet by Rdrain with fixed Rsource
« Reply #23 on: January 22, 2021, 01:38:04 PM »
Sorry this was a double post. Removed it.
« Last Edit: January 22, 2021, 01:41:17 PM by hans h »

antonis

Re: Biasing jfet by Rdrain with fixed Rsource
« Reply #24 on: January 22, 2021, 01:40:12 PM »
The whole impedance thing often has me puzzled. For example: input impedance of a stompbox depends on inp. impedance of the first transistor, AND on the value of resistor connected in series with input, AND on the value of resistor connected from input to ground (also anti-popping resisistor). Quite complex to me.


Just apply Kirchoff's circuits laws (KCL & KVL) for each amplification (active) stage..
https://en.wikipedia.org/wiki/Kirchhoff%27s_circuit_laws

Hint: Power supplies should be considered AC grounds and JFETs (devices) impedance infinite..

« Last Edit: January 22, 2021, 01:41:51 PM by antonis »
"I'm getting older while being taught all the time" Solon the Athenian..
"I don't mind  being taught all the time but I do mind a lot getting old" Antonis the Thessalonian..

antonis

Re: Biasing jfet by Rdrain with fixed Rsource
« Reply #25 on: January 22, 2021, 01:43:06 PM »
Could you plz post a particular circuit schematic..??
"I'm getting older while being taught all the time" Solon the Athenian..
"I don't mind  being taught all the time but I do mind a lot getting old" Antonis the Thessalonian..

hans h

Re: Biasing jfet by Rdrain with fixed Rsource
« Reply #26 on: January 23, 2021, 09:16:21 AM »
Hi Antonis,






After the information I got from all of you, this will be my approach:
1) 7thheaven: its already in the box so I can only fiddle with the trimmers and try different jfets. For this one I'll take the approach of GibsonGM: first bias to 9V. Next I use my "scope", trim each stage up or down and listen to the effect. My plan was to go down from 9V on the first stage, up from 9V on the second etc. This should in theory give me a bit more asymmetric clipping because the signal is inverted at each stage.

2) Supro 1606: I want to get this out on my breadboard. I'll start with two versions: version 1: use Rsource from the schematic, only change drain resistor (9V/ by ear) like on the 7thheaven. Version 2) compute Rsource AND Rdrain following the approach of Antonis/ Rob and afterwards the approach of Paul (for Paul's approach I'll probably come back for more advice). Goal of this all is to hopefully have a fun circuit and learn a lot about jfet biasing.

@ Rob: is it correct that I only see a png version of your spreadsheet?

hans h

Re: Biasing jfet by Rdrain with fixed Rsource
« Reply #27 on: January 23, 2021, 02:09:05 PM »
@paul: I think something is off with my j201s. Using the stock Rsource (because it is already soldered on Vero), I have to use between 62 and 220(!) k Rdrain. This seems unreasonably high. Might this cause impedance mismatch between the stages? I feel that the tone is less clear (bit muffled) than it ought to be.

Rob Strand

Re: Biasing jfet by Rdrain with fixed Rsource
« Reply #28 on: January 27, 2021, 07:19:52 PM »
Quote
@paul: I think something is off with my j201s. Using the stock Rsource (because it is already soldered on Vero), I have to use between 62 and 220(!) k Rdrain. This seems unreasonably high. Might this cause impedance mismatch between the stages? I feel that the tone is less clear (bit muffled) than it ought to be.

If you look at the table in Reply #16, which is roughly a J201,  you can see that as RS increases the required RD increases.
The table of RS and RD give you an overall view of how things are related.

Q2:  RS = 4.75k,  closest value in table RS = 4875,  requires RD = 44k
Q3:  RS = 10k,  closest value in table RS =10110, requires  RD = 78k

All high RD values.

The thing is JFET parameters vary from unit to unit.  To make things worse, some of the J201's you buy these days are not representative of the "real" J201's.   In this case the table doesn't  quite match your actual parts.

Q2: If you mess with R9 = 4.75k it could upset something since it works in conjunction with R10 and C4;  they would need to be tweaked.

Q3:  The lack of clarity would come about when R13 need to be set to a high resistance.   The cap C10 causes HF roll-off but the roll-off gets worse when R13 is set to a high value.    So perhaps set R13 to the mid position (50k) then adjust R14 to get the correct drain voltage.


You do get the loss of clarity issue with Q2 from R9 and C9 but you need more changes to fix it.
« Last Edit: January 27, 2021, 07:24:38 PM by Rob Strand »
The internet:  answers without the need for understanding.

hans h

Re: Biasing jfet by Rdrain with fixed Rsource
« Reply #29 on: January 31, 2021, 02:00:03 PM »
Thanks Rob, that is really helpful. One other thing I did not know is that the supply voltage changes the required Rdrain. I now went back to a 9v power supply which lowers the Rdrain quite a bit and therefore helps with the clarity issue quite a bit. The other thing I did was try every j201 in those two positions (q2 and q3). I selected the ones that gave me the lowest Rdrain.

Also tried 2n4548. This gave substantially lower Rdrain values but I lost the high gain, which is what I built this pedal for in the first place. For now i stay with the j201's and 9v power supply.

I'll play around with it a bit when the kids are not home to see how I like it. If it's not clear enough yet I'll also solder in a socket for r14.

Thanks a lot, Hans

antonis

Re: Biasing jfet by Rdrain with fixed Rsource
« Reply #30 on: January 31, 2021, 02:31:52 PM »
One other thing I did not know is that the supply voltage changes the required Rdrain.

It's just Ohms Law.. :icon_wink:

For a given Drain-Source current and also given Drain bias voltage (VDD/2 say), Drain resistor value is directly proportional to power supply voltage..
e.g. for 1mA Drain current and +9V power supply, you need a 4k5 Drain resistor for Drain biasing at 4.5V (VDD/2) where for 18V power supply you need 9k Drain resistor for Drain biasing at 9V (VDD/2)..

CS amp gain is directly proportional to Drain resistor value(*) (either -gmXRDrain or RDrain/RSource) so for a given working current gain is directly propotional to power supply voltage.. :icon_wink:
(*) in parallel with any succeeding load..
"I'm getting older while being taught all the time" Solon the Athenian..
"I don't mind  being taught all the time but I do mind a lot getting old" Antonis the Thessalonian..

Rob Strand

Re: Biasing jfet by Rdrain with fixed Rsource
« Reply #31 on: January 31, 2021, 07:55:09 PM »
Quote
Also tried 2n4548. This gave substantially lower Rdrain values but I lost the high gain, which is what I built this pedal for in the first place. For now i stay with the j201's and 9v power supply.
2N5484's yes?

Anyway, most of the common JFETs will lose a bit of gain compared to the J201's when the source resistor is not bypassed.

You can increase the gain on stages where the source resistor is not bypassed using one of these methods,





However it can get a bit messy if there's already caps, like your Q1,  or caps + resistors, like your Q2.

You should be able to tweak the source resistor (and corresponding drain resistor) on the J201 to get a good result.
The internet:  answers without the need for understanding.

hans h

Re: Biasing jfet by Rdrain with fixed Rsource
« Reply #32 on: February 07, 2021, 02:50:42 AM »
Thanks Rob,

Another helpful comment. I knew about bypassing using a cap but had not considered it. Not so practical for my current build, but really handy in tuning the supro 1606 schematic that I have in mind. Never noticed that the cap is sometimes in series with resistance and sometimes in parallel. What's the practical difference?

antonis

Re: Biasing jfet by Rdrain with fixed Rsource
« Reply #33 on: February 07, 2021, 05:00:55 AM »
Never noticed that the cap is sometimes in series with resistance and sometimes in parallel. What's the practical difference?

Practically none.. :icon_wink:

C3 in series with R5 bypass R4 where 68μF bypasss 820Ω while been in series with 180Ω..
(in the mean of, for DC purpose, R4 is considered Emitter resistor where 180Ω + 820Ω is also considered the same..)

For R4=1k, R5=180Ω and C3=68μF bias point and Gain/Frequency responce are the same for both configurations..
« Last Edit: February 07, 2021, 05:39:00 AM by antonis »
"I'm getting older while being taught all the time" Solon the Athenian..
"I don't mind  being taught all the time but I do mind a lot getting old" Antonis the Thessalonian..