Author Topic: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging  (Read 36356 times)

StephenGiles

Re: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
« Reply #60 on: September 22, 2012, 09:49:49 AM »
I agree with the you Ton, especially when the guitar is battling on stage with a bass player also trying to play lead and an over enthusiastic drummer! I think it is more of a recording tool than a stage tool as far as the TZF is concerned.
"I want my meat burned, like St Joan. Bring me pickles and vicious mustards to pierce the tongue like Cardigan's Lancers.".

DiyFreaque

Re: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
« Reply #61 on: February 28, 2013, 09:45:19 PM »
I'm with Ton - I like the Shanghai Bellings.  I used to look at the whole MN32XX family with a tad bit of disdain, but I've since discovered that they can do nice things for you if you're really nice to them.

I also think through zero can be really cool even on fairly sedate input signals.  The more harmonically rich the input, the more pronounced the effect, but even on "smooth" tones, the effect is far spacier to me than regular flanging.

These are Shanghai Belling BL3207s performing TZF on a fairly sedate (harmonically speaking) synthesizer piece.  It's positive TZF - I'm still trying to wrap my head around making that total drop in signal at negative through zero to do anything musical with it using a synth.  It's just the synth through the circuit to the recorder, no multi-tracking (or much musical talent, for that matter).

http://www.birthofasynth.com/sstites/HEADLine_10_TZF_1.mp3



stm

Re: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
« Reply #62 on: February 05, 2015, 08:22:55 PM »
This is an old thread (10 years and a bit more), however I get asked from time to time about the schematics that have dissappeared because they were uploaded to a free image server.

I have improved the circuit a good deal in terms of noise performance, less variation with respect to parts tolerances, and using a single value of capacitors.  I'm ready to post the circuit and I tried to upload it to the Layouts Gallery (STM Guitar FX) so it will survive longer than in a free image hosting site, however during the past two days I am getting an error message #7 (whatever that is) when trying to upload the file.  The file is around 35 kbytes in PNG format, so it is not a matter of size :icon_eek:

Have anybody have experienced a similar issue or have a clue as to what could be causing this?
« Last Edit: February 06, 2015, 11:41:22 AM by stm »

Tony Forestiere

Re: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
« Reply #63 on: February 05, 2015, 08:31:24 PM »
Have find another hosting company or do something with the gallery. Out of space.
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"Whoso neglects learning in his youth, loses the past and is dead for the future." Euripides
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stm

Re: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
« Reply #65 on: February 06, 2015, 07:27:54 AM »
This is a revised version of the analog delay circuit.

You can cascade four identical circuits (for a total of 8 opamps) to obtain a fixed 0.5 msec delay up to 6 or 7 kHz.

This revision has several improvements over the previous circuits, including:

- The basic building block ia a 4th order section instead of a 7th order section, so the resulting response is less affected by component tolerances
- The building block topology has unity gain and does not need a gain recovery stage at the end, therefore being less noisy
- The capacitors are all of the same value, and less different resistor values are needed, therefore making the build easier and less prone to error

In any case this circuit requires precision components, 1% metalfilm resistors and 5% or better capacitors.  Failing to do so will result in dips/peaks in the amplitude response which will accumulate if several cascaded stages are used.

« Last Edit: February 06, 2015, 07:35:51 AM by stm »

~arph

Re: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
« Reply #66 on: February 06, 2015, 11:17:54 AM »
Nice!

(so for 500ms I would just use 8000 opamps  8)

stm

Re: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
« Reply #67 on: February 06, 2015, 11:45:56 AM »
Nice!

(so for 500ms I would just use 8000 opamps  8)

Yes, or a 170 meter (560 feet) pipe with a speaker in one end and a mic at the other  :P
« Last Edit: February 06, 2015, 11:50:45 AM by stm »

rx5

Re: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
« Reply #68 on: September 18, 2021, 11:38:35 AM »
This is a revised version of the analog delay circuit.

You can cascade four identical circuits (for a total of 8 opamps) to obtain a fixed 0.5 msec delay up to 6 or 7 kHz.

This revision has several improvements over the previous circuits, including:

- The basic building block ia a 4th order section instead of a 7th order section, so the resulting response is less affected by component tolerances
- The building block topology has unity gain and does not need a gain recovery stage at the end, therefore being less noisy
- The capacitors are all of the same value, and less different resistor values are needed, therefore making the build easier and less prone to error

In any case this circuit requires precision components, 1% metalfilm resistors and 5% or better capacitors.  Failing to do so will result in dips/peaks in the amplitude response which will accumulate if several cascaded stages are used.



hi STM

could you please re-upload this?

going the op-amp route would be much practical than going with the now NOS 3101/3007. would like to try this out on my buffered mistress.  :icon_mrgreen:

cheers
BE d Bezt, Urz D Rezt... RoCk ON!!!

rx5

Re: Schematic of 0.5 msec Analog Delay for Through-Zero Flanging
« Reply #69 on: September 19, 2021, 11:38:34 AM »

 ok nvm.. found *more*stuffs on the net.. and sim' d it on Ltspice. yep flat response and unity gain at the inverted output. this was with TL082 and resulted in 100uS phase delay per op-amp. total of 400uS per quad chip. add another dual for the signal inversion & strong midpoint voltage.

now I can still remember the older 741 and 324.. how where they being clunky devices? slow?? would it add up the phase delay?  :icon_mrgreen:

hmmmmmmm

 
BE d Bezt, Urz D Rezt... RoCk ON!!!