Daisy chaining AD5262 digipot

[MrStab]

Hi,

I've successfully managed to bit-bang (oo-er) the awkward 9 bits required by the dual-gang AD5262 digital pot, and wiper position updates as expected on pots directly connected to the MCU, but when daisy-chaining, I get what seems like a very rude hand gesture from the IC. I'm sending two 18 bit words (as i'm changing all gangs on two dual-gang digipots). SDO falls and rises as expected, but sends an empty byte each time.

Please see images. I can't figure out how to get rising and falling edge to capture at the same time on my rubbish scope, which does inconvenience things a bit (the SDI pin is low when idle, but SDO is always pulled up high with a 3k9 resistor).




The appropriate CS pin doesn't rise again until after all 18 bits have been sent. PR and SHDN pins high, and SCK is being sent to both ICs. Even without artificial delays, my slow 8MHz AVR exceeds all minimum timing specs, as far as I can tell.

Datasheet is here (daisy-chaining detailed on page 16): http://www.farnell.com/datasheets/686036.pdf
I'd sign up for the AD forum, but that would be significantly more sterile and less fun.

cheers for any help! so close to getting a pretty kewl thingy working here.

[MrStab]

Not sure what crazy nonsense i was spouting about my scope! I had just woken up!
Here's SDI and SDO, and CS and SDO on the same frames.





I can only assume damage at this point, perhaps to the inverter feeding the gate on the SDO output (as the level still seems affected by CS).

[ElectricDruid]

Past experience tells me that this kind of problem is almost always getting the SPI mode set up correctly. There are four possible modes (iirc) with the rest state of the line being one of two options, and (i think) the polarity of the clock being the other. In certain *wrong* combinations, things basically work, but you lose data because the data is being read when the clock goes low instead of when it goes high or whatever. You think it's working, but it's not. Tweak it again and it'll come properly to life.

In short, you have to try all four ways until you get it right. It should be possible to hit the correct combination sooner than that, even just by dumb luck, but I never seem to manage!

[MrStab]

Hi Tom,

Thanks for the reply! On a non-daisy-chained pot, I have smooth, anticipated control of a volume pot. I wanted to make sure i had that part correct first, so i tested on something more simple instead of multiple gangs somewhere more complicated.

 (I did have a "hmm... it kinda works...?" situation like you describe yesterday, when i forgot to bit-shift back to the right port i was using for master SDI!)

Anyways, i just noticed that the datasheet said i should connect the SDO-SDO pull-up to "VDD", whereas i had it connected to the logic voltage of 3V. I was hesitant to connect it to VDD as it's 9V, and SDI is rated for 7V max, but i gave it a go and this happened:


Can't yet find this caveat in the datasheet, but it's probably in there. So current question is: "To hell with the SDI rating and throw anything up to max VDD in there, or the real problem is that 3V is just too low?"

[ElectricDruid]

Ok, having one working first is a very good start.

I've also screwed up going from "one" to "many" by not paying attention to which end of the data finishes up at which pot, or not paying attention to which end of things data is getting shifted out of. There I am, tweaking my test pot, measuring the resistance of one of my digipots, and getting nothing happening, when all the time I was tweaking a different pot. Or alternatively, tweaking, and seeing movement, but it doesn't make sense because the data is backwards.

SDO to SDO isn't right. SDO from one chip goes to SDI of the next. Output from one to input of the next - logical, right?

The chip select and clock lines, however, *are* all connected together, so it's easy to get in a tangle with this stuff.

[Ice-9]

SDO to SDO isn't right. SDO from one chip goes to SDI of the next. Output from one to input of the next - logical, right?

The chip select and clock lines, however, *are* all connected together, so it's easy to get in a tangle with this stuff.

Exactly this, the first thing to look at.