Author Topic: FET in EQD Bellows  (Read 392 times)

Vivek

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FET in EQD Bellows
« on: June 23, 2022, 09:03:07 AM »
What does the FET in EQD Bellows do ?



antonis

Re: FET in EQD Bellows
« Reply #1 on: June 23, 2022, 09:24:26 AM »
"I'm getting older while being taught all the time" Solon the Athenian..
"I don't mind  being taught all the time but I do mind a lot getting old" Antonis the Thessalonian..

Vivek

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Re: FET in EQD Bellows
« Reply #2 on: June 23, 2022, 11:31:31 AM »
Thanks Antonis and Paul !

iainpunk

Re: FET in EQD Bellows
« Reply #3 on: June 27, 2022, 11:02:30 AM »
people on reddit seem to strongly disagree with the statement that the JFET works as a diode here, basically making it a fancy Bazz Fuss. i got some spicy and hate filled DM's...

cheers
friendly reminder: all holes are positive and have negative weight, despite not being there.

cheers

Rob Strand

Re: FET in EQD Bellows
« Reply #4 on: June 27, 2022, 08:12:16 PM »
people on reddit seem to strongly disagree with the statement that the JFET works as a diode here, basically making it a fancy Bazz Fuss. i got some spicy and hate filled DM's...

cheers
In the idle state or for small signals I suspect the JFET acts as a diode.   The collector will be about 0.65V above the base, so the JFET gate voltage is positive.  The JFET is essentially on and the JFET gate diode is conducting.

Things could change when the circuit is pushed into clipping.

For strong negative input swings the transistor is off.   The gate is pulled to a positive voltage.   The JFET is on.  The gate diode essentially acts as a clipping diode.

For strong positive input swings the transistor.   The transistor suppose the transistor saturates: the collector will sit about 0.8V above the base emitter,  and the base will sit about 1.3V above the emitter.    So under saturation the base sits at a voltage above the collector.   That will do two things:
- sets the gate voltage to 0.5V below the source
- reverse biases the gate diode.   At this point you might think there's no base current from the diode, while that's true we still get base current from the strong positive input signal.

So what will the JFET do now?  It comes down to specifics.
The spec'd JFET has a low-ish VP (-0.7V to -1.6V), IDSS = 4mA to 20mA, and gfs = 11000uS min.  We might expect most units to end-up around VP = -1V, IDSS = 12mA, gfs= 24000uS.

For info on JFETs see,
https://en.wikipedia.org/wiki/JFET
and page 4,
https://global.oup.com/us/companion.websites/fdscontent/uscompanion/us/static/companion.websites/9780199339136/pdf/bonustopics.pdf

When then transistor is saturating the gate is 0.5V below the source.  If the input signal is positive and the drain is positive.  Suppose the source voltage get high enough to reach the active region (pinch-off/saturation) then the drain current would be ID = IDSS(1-|Vgs/VP|)^2 = 12e-3*(1- 0.5/1)^2 = 3mA.

With the 10k gate resistor present that means the input would need to be enormous, > +10V.  So it's unlikely the JFET would operate in the active region and more likely to operate in the triode region.   To simplify assume Vds is smaller than VP, then ID ~ (2 IDSS/VP)(1-VGS/VP)VDS  which means the JFET looks like a resistor  Rds = (VP/(2 IDSS)) / (1-VGS/VP) = 1/(2*12e-3)/(1-|0.5/0.7|) = 150 ohm.   That region will hold up to a current of Vds_max = VP but the approximation doesn't, ie. ID = 1/150 = 6.7mA.  The fact it's higher than 3mA means the approximation isn't great but if we limit Vds to 0.5V then we end-up ID=3mA and the JFET looking like a 167 ohm resistor (still a low value).

Putting the analysis simplifications aside, for strong positive inputs the JFET will look like a low valued resistor and the gate diode with be reversed bias.   The 10k input resistor will largely determine the behaviour.   So based on that, it's sure looking like the JFET is just acting as a Bazz-Fuzz diode.

If the JFET had a smaller VP then the currents would be lower.   If we could get a JFET will a VP lower than 0.5V then perhaps then the JFET would be able to act as a kind of limiter.    Playing around with stuff at this level is a job for SPICE.

I'll throw out a challenge for someone to do a SPICE sim:  show for VP=1V IDSS=12mA the JFET acts as a diode and for a VP around 0.5V or less show something happens for strong positive inputs.

For guitar level inputs I doubt you will see any limiting effect from the JFET unless you do some very silly fine tuning of VP is the small decimal places.
« Last Edit: June 28, 2022, 08:11:16 PM by Rob Strand »
Send:     . .- .-. - .... / - --- / --. --- .-. -

Vivek

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Re: FET in EQD Bellows
« Reply #5 on: June 28, 2022, 04:44:21 AM »
I will properly read Rob's post later

But wanted to take this opportunity to thank various Elmers and gurus on this site, for their kindness in sharing viewpoints, knowledge, experience

It is always so invigorating and a humble learning experience to read the posts of the many great people on this forum.

iainpunk

Re: FET in EQD Bellows
« Reply #6 on: June 28, 2022, 07:19:30 AM »
I will properly read Rob's post later

But wanted to take this opportunity to thank various Elmers and gurus on this site, for their kindness in sharing viewpoints, knowledge, experience

It is always so invigorating and a humble learning experience to read the posts of the many great people on this forum.
i want to echo this. those people on this forum are like rockstars to me!

cheers
friendly reminder: all holes are positive and have negative weight, despite not being there.

cheers