Of BBD's & CCS's

Started by Scruffie, July 04, 2022, 10:22:23 AM

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Scruffie

I just wondered if anyone had scoped out the impact of a CCS on a BBD output in place of the source resistor and if it had any beneficial impact on signal level loss vs. clock frequency?

Don't have my equipment at the moment so can't poke about my self and thought it might be quite handy for some flanging action if it offered any improvement at all.

Mark Hammer


Scruffie


StephenGiles

I read something about this a few years ago - but where?
"I want my meat burned, like St Joan. Bring me pickles and vicious mustards to pierce the tongue like Cardigan's Lancers.".

Scruffie

Quote from: StephenGiles on July 04, 2022, 03:23:06 PM
I read something about this a few years ago - but where?
The old Phillips datasheet suggests it for compensating the insertion loss on the TDA1022, but I don't recall any mention of its impact on signal loss in relation to clock frequency.

StephenGiles

Yes I did have a Philips circuit for that. Can't get at my PC at the moment because it's doing z check disc on an HDD which is very slow.
"I want my meat burned, like St Joan. Bring me pickles and vicious mustards to pierce the tongue like Cardigan's Lancers.".

puretube

IIRC, those CCS-solutions only concerned the first technology-generations of BBDs (&CCDs) in the late sixties/early seventies ...

Scruffie

Quote from: puretube on July 06, 2022, 06:29:32 PM
IIRC, those CCS-solutions only concerned the first technology-generations of BBDs (&CCDs) in the late sixties/early seventies ...
Yes, they were for recovering the insertion loss in that application, but, nothing to stop them being used on 'modern' BBD's and I'm wondering if there might be some fringe benefit from doing so :icon_question:

Every little helps when it comes to BBD design!

StephenGiles

#8
Is this any help? A kind man at Philips sent me this "by post" back in the 1980s!!


"I want my meat burned, like St Joan. Bring me pickles and vicious mustards to pierce the tongue like Cardigan's Lancers.".

danfrank

#9
Hi Scruffie.
Let me start by saying that I've never used a CCS on BBDs but I have used them in tube circuits, namely in gain stages. For example, a 12AX7 gain stage will get nowhere near a gain of 100 with a simple resistor load, it might get up to 75 or so... With a CCS load, it will get very close to 100. CCSs make near perfect loads in tube gain stages. I think they've also been used in the outputs of TDA1541A DAs with great results.
It's my understanding that the output resistor in BBDs is needed in order to make an output signal (voltage)... This is basically the same thing as a triode gain stage, a resistor is needed in order to create an output voltage. The problem with output resistors is that when the voltage (or current) changes at the output, it's not linear at the extremes (tube curves anyone?)... The CCS, being a near perfect (infinite) load really does wonders for linearity of the circuit. I'm sure this applies to BBDs as well.
I've probably added nothing new here and with my long windedness, I kind of forgot what your original question was... Ha!
I guess if you're looking for the ultimate in BBD linearity, a CCS would probably help. I don't think it would help much with the lower output at increasing frequencies that BBDs suffer from. I think those losses come from elsewhere.

Scruffie

Quote from: StephenGiles on July 08, 2022, 06:55:30 AM
Is this any help? A kind man at Philips sent me this "by post" back in the 1980s!!



Thanks Stephen, an example of the old chips needing one for insertion loss, 6 chips for 100mS of delay!

Quote from: danfrank on July 09, 2022, 12:19:11 AM
Hi Scruffie.
Let me start by saying that I've never used a CCS on BBDs but I have used them in tube circuits, namely in gain stages. For example, a 12AX7 gain stage will get nowhere near a gain of 100 with a simple resistor load, it might get up to 75 or so... With a CCS load, it will get very close to 100. CCSs make near perfect loads in tube gain stages. I think they've also been used in the outputs of TDA1541A DAs with great results.
It's my understanding that the output resistor in BBDs is needed in order to make an output signal (voltage)... This is basically the same thing as a triode gain stage, a resistor is needed in order to create an output voltage. The problem with output resistors is that when the voltage (or current) changes at the output, it's not linear at the extremes (tube curves anyone?)... The CCS, being a near perfect (infinite) load really does wonders for linearity of the circuit. I'm sure this applies to BBDs as well.
I've probably added nothing new here and with my long windedness, I kind of forgot what your original question was... Ha!
I guess if you're looking for the ultimate in BBD linearity, a CCS would probably help. I don't think it would help much with the lower output at increasing frequencies that BBDs suffer from. I think those losses come from elsewhere.
Yeah, the drop off at high clock frequencies is the result of low pass, no (simple) cure for that, but if you've ever looked at the gain output of a SAD1024 for example, it's actually quite bumpy across its sweep, so from your middle paragraph, you seem to expect the same as me, a CCS might help with the non-linearity of gain on them, which could potentially be an improvement for flangers for that fabled 50/50 mix.

anotherjim

Stephens posted Philips scheme has another interesting technique. The clock flip-flops seem to include a phase switching gap to prevent edge overlap in the BBD charge transfer switching.


Scruffie

Quote from: anotherjim on July 09, 2022, 07:54:48 AM
Stephens posted Philips scheme has another interesting technique. The clock flip-flops seem to include a phase switching gap to prevent edge overlap in the BBD charge transfer switching.
So it does! I hadn't noticed that.

There's also another technique in(verting) play there...

Rob Strand

#13
Both the current source idea and clock dead-time generator are in the TDA1022 datasheet,
https://pdf1.alldatasheet.com/datasheet-pdf/view/87606/ETC/TDA1022.html

The dead-time might be a quirk of the TDA1022 however in the back of my mind
the Panasonic clock chips did a few extra things as well.

The claim (bottom of page 4) is the current source reduces the signal loss of the device.   
I suspect there is loss with a load resistor because the resistance of the output MOSFETs form
a resistive voltage divider with the bias/load resistor.   The current source load is high impedance and avoids
the divider - at least the extent that the output loads can be increased, for example to 100k
like that old Philips schematic.

The SAD1024 etc had a slightly different output stage:
https://cdn.datasheetspdf.com/pdf-down/S/A/D/SAD1024_EGGReticon.pdf

If you look at figure 12b they offer different output solution.   As I see it this is not a current source.
It's like they are forming a feedback amplifier at the output.  Notice how the chip VDD pin is fed via
the base of the transistor.

In general be careful about copying stuff from one BBD circuit to another.   Some BBD devices are PMOS and some NMOS and you will see the bias resistor is moved from ground to +VDD.  Take a look at the various Boss pedals and you can see this.
Send:     . .- .-. - .... / - --- / --. --- .-. -
According to the water analogy of electricity, transistor leakage is caused by holes.

Scruffie

#14
Yeah, the MN3101 has dead time too as I recall (I think in the block diagram it's called wave shape conditioning or some such).

Indeed, P vs. N channel devices but, I know the current source improves gain with an MN3207 as I used that in a pinch once for recovery when I wanted to reduce input level, but still, not my original question, does it improve output signal level linearity over the clock range to any degree over a standard source follower resistor.

Rob Strand

Quote from: Scruffie on July 09, 2022, 08:46:36 PM
still, not my original question, does it improve output signal level linearity over the clock range to any degree over a standard source follower resistor.
I don't know the answer.  It's the type of thing you would really need to measure.

If you look at the plots in the datasheets that behaviour isn't consistent in the sense of rising and falling gains with clock frequency.  You would think something complex is going on.   I can't imaging the last stage fixing the errors in the ways of 1024 BBD transfers.   There's cases where a current source load can help the flatness driving into a capacitive load but that's not what's happening here.   The Philips example is outright resistive loading, so no mysteries there.

The actual innards of a BBD is different to the simple schematics shown in the datasheets.   Back in the days of BBD development, say early 70's, Philips and the guys who founded Reticon produced documents with a lot more details.

ElectricDruid and few other's (maybe yourself  :) ) had a some discussions a few years back.   They have put a lot more time into it than myself.   There were comments about the clock waveforms affecting the behaviour of the BBD.    That seems very likely.   It might even mean the plots in the datasheets are only applicable for the specific clock waveforms used in test set-up in the datasheets.
Send:     . .- .-. - .... / - --- / --. --- .-. -
According to the water analogy of electricity, transistor leakage is caused by holes.

Scruffie

Quote from: Rob Strand on July 09, 2022, 09:27:43 PM
Quote from: Scruffie on July 09, 2022, 08:46:36 PM
still, not my original question, does it improve output signal level linearity over the clock range to any degree over a standard source follower resistor.
I don't know the answer.  It's the type of thing you would really need to measure.

If you look at the plots in the datasheets that behaviour isn't consistent in the sense of rising and falling gains with clock frequency.  You would think something complex is going on.   I can't imaging the last stage fixing the errors in the ways of 1024 BBD transfers.   There's cases where a current source load can help the flatness driving into a capacitive load but that's not what's happening here.   The Philips example is outright resistive loading, so no mysteries there.
Somewhere I had some real world measurements of a couple of chips that someone else provided and I confirmed and it was a much bumpier ride than the datasheet's provide (which is more of an average) with odds dips and peaks here and there which prompted the original question... several years later out of nowhere over my morning coffee :D

I doubt the average gain can be fixed all that much without external intervention (TC Electronic took a rectified voltage from the clock to feed the Vgg pin of the 3007 to adjust the gain in their chorus/flanger along with a VCA) but smoothing to closer match the datasheet specification would be nice.

You raise a good point, I vaguely recall the clock dead period thread, I hadn't factored that in to the aforementioned chip measurements, perhaps that was at play.

Rob Strand

QuoteSomewhere I had some real world measurements of a couple of chips that someone else provided and I confirmed and it was a much bumpier ride than the datasheet's provide (which is more of an average) with odds dips and peaks here and there which prompted the original question... several years later out of nowhere over my morning coffee :D
:)

From the old Philips/Reticon docs I remember the real BBD circuit had feeds from the power rails.  It's not hard to imagine that imperfect bypassing of the power supplies could have an effect.   Perhaps made worse if the clock driver and BBD share the same power rails and ground.   With 1000 stages it also not hard to imagine how tiny and normally ignored secondary effects get multiplied up into a noticeable effect.   The chip designers have done great job coming up with something that works at all!
Send:     . .- .-. - .... / - --- / --. --- .-. -
According to the water analogy of electricity, transistor leakage is caused by holes.

puretube

#18
Interestingly, most TDA1022-schemos show no symmetry-pots at the output(-s), or only at the last BBD of a row of them. Maybe it seemed unneccessary while using non-overlapping clocks, or  while using less spikey trapezoidal clock-pulses ...
In the history of BBD/CCD-development there were various improvements or alterations concerning the length of the clock-pulses (some including extra S&H stages before and/or after the BBD-stages) up to a statement I read somewhere, that even sinusoidal clocking was usable.

Scruffie

Quote from: puretube on July 10, 2022, 03:53:38 AM
Interestingl, most TDA1022-schemos show no symmetry-pots at the output(-s), or only at the last BBD of a row of them. Maybe it seemed unneccessary while using non-overlapping clocks, or  while using less spikey trapezoidal clock-pulses ...
In the history of BBD/CCD-development there were various improvements or alterations concerning the length of the clock-pulses (some including extra S&H stages before and/or after the BBD-stages up to a statement I read somewhere, that even sinusoidal clocking was usable.
Most I've seen have used an inverting stage between chips, necessary for the reduced gain even with the CCS but has the side benefit of helping with the clock cancellation anyway so it could just be a trim saving measure, Stephen's schematic only has one bias trimmer for 6 chips which is... bold.

I really must try and find some of these early technical notes.