Def Con 1 in LTSpice transient analysis

[Digital Larry]

I've put the important bits of a Boss Slow Gear schematic into LTSpice.  Depending on the value of the "attack" resistor setting, it will either simulate quickly, or start showing "Def Con 1" as soon as the exciting part starts and take quite a bit longer to complete (with some glitches at the beginning of the tone burst).  I've read a bit and people complain about op-amp models or JFET models or whatever.  Used the most generic models of everything at this stage.  I don't want to spend years of trial and error here.  Any suggestions?

Edit: I actually don't know what the circuit is sensitive to.  Changing different things results in different errors etc.  I'm mostly focused on the pluck detector and its behavior over time to different types of input signals.  I've ripped out the JFET and beyond just to focus on this, it seems a little happier.

I'm open to other tools but again I don't want to spend years getting there.  I'm also open to paying for something although my budget is probably in the $100 range.

Thanks!

DL

[PRR]

What is "def con"?

When SPICE slows it has often run into infinity or zero. An unspecified opamp may be gain of 10^6 and infinite bandwidth, and that is fine until the clipping starts.

[Digital Larry]

What is "def con"?

When SPICE slows it has often run into infinity or zero. An unspecified opamp may be gain of 10^6 and infinite bandwidth, and that is fine until the clipping starts.

Def con is the error message that displays in the status area.
I'll see if taking the op amp out of clipping helps.  It doesn't sound like much fun.   

[MikeA]

...Used the most generic models of everything at this stage....

Sometimes using a specific part model for active components, rather than a generic (2N3904 vs. NPN for example) will resolve these issues, it seems that specific parts are less likely to be modelled as "perfect" parts that can go to infinity or zero as PRR said.  Op amps are particularly prone to this in my sims.

[Rob Strand]

IIRC, D2 should be a zener.  You could even place a fixed DC source at that point.  That's going to fix the JFET biasing.
[confirmed, 5.6V zener]

The biggest help for weird spice behaviour is to set initial conditions.   Other times I add large resistors to ground here and there.   I tend to give the sims a nudge when they simulate slowly or don't converge consistently since I tend to run them many times when tweaking a circuit.

It also would help if you set the trimpots so the pedal performance is within spec. as per Service manual.

Another thing that might help, at least to start with, is to wire the emitters of the two rectifier transistors to a fixed DC voltage.   So knock out the single diode and everything upto and including the trimpot.   There might be some issue with that bias network reaching a steady-state voltage.   Alternatively, setting the voltage on that 10uF using initial conditions might help.

First things first, fix up D2.  Maybe it will all fall into place after that.

[PRR]

Def con is the error message that displays in the status area.

Ah. I confess I have not abused LTspice as much as I maybe could have? (I've pounded PSpice into the weeds on 20 minute runs, but "defcon" must be a LTspice thing.)

I suppose you have web-searched for defcon + ltspice clues?

[Digital Larry]

I simplified the circuit a bit.  The op-amp gain is (1 + 1 Meg/3.9K) or or, err. cough... a bit over 250 in the mid band.

I'm messing with the attenuation resistor on the op-amp's input circuit (circled).  Much above here and I get DEF CON 1 beep beep beep.  I added the beeps just for drama.

This is nowhere near clipping!

[Vivek]

I dont know much about this

But when I have similar issues

Sometimes, using the generic opamp models,

or using specific opamp models but at different levels of accuracy

helps to remove the situation where suddenly the model takes too long to compute.

[Digital Larry]

I tried a couple different op-amps.  I can try more, there are only 12 million of them.  1 is bound to work.   

[Rob Strand]

I tried a couple different op-amps.  I can try more, there are only 12 million of them.  1 is bound to work.   

Based on your last sim the junk is present on the *input side* of the divider.  From the waveforms the opamp is working and just amplifying what is going in;  from before the divider to the opamp output is a gain of about 2.

Try removing the divider and the opamp and feeding the buffer straight into Q3; DC coupled it will bias OK.

Alternatively you can just replace the path from the buffer upto C14, R22 with a voltage controlled voltage source (spice E gain and set the overall gain).   Be aware the output of the E source will no longer clip.

One thing that stands out is the divider is 680/(680+100k) = 1/150, and the opamp gain is (1+1M/3k9)=257.
What that's doing is making the node voltages in the numeric solution spaced further apart.   I'll admit when referenced to a ground node that's normally not a problem.   If there's a problem elsewhere in the circuit like the opamp model, or subtle issues around D4, Q4, Q5 then the spaced voltages push the numeric solver over the edge and the solution becomes very noisy (due to numerical issues).

[Digital Larry]

Interesting theory Rob!

I dialed down the generator level by a factor of ten and reduced the attenuation a bit.  Here's where I get the glitch.  It looks like it happens when one of the phase splitter emitter followers start conducting.

If I ground Q5's base, it works fine (although I don't get that phase of the rectifier output).





PRR there's all sorts of discussions about it.  I've yet to stumble into a conclusive solution.

https://www.reddit.com/r/ECE/comments/ctc1qf/lt_spice_def_con_1/

[Rob Strand]

I dialed down the generator level by a factor of ten and reduced the attenuation a bit.  Here's where I get the glitch.  It looks like it happens when one of the phase splitter emitter followers start conducting.

If I ground Q5's base, it works fine (although I don't get that phase of the rectifier output).

I had a feeling it's related to that area around Q4, Q5, D4.   There a lot of capacitively coupled stuff and together with the diode.

What about adding a larger resistor (100MEG/10MEG/1MEG) from the emitters of Q4, Q5 to ground?
I suspect it might come good.

PRR there's all sorts of discussions about it.  I've yet to stumble into a conclusive solution.

The cause might be numerical but the actual root-cause in the circuit can vary widely.   There's no specific thing that causes it unless you get down the numerical solutions not converging.

I've got some simple examples where changing the order of L and R in an series L+R network can affect the results, and interestingly using the built-in series R in the LTspice model avoids the problem.  In that case it boils down to the smaller voltages being closer to ground.   The build-in L+R in LT spice seems to enter a complex number directly into the matrix for ZL and avoids creating a voltage node in the solution matrix altogether.

[PRR]

Why is the phase-splitter biased to nominal V/2? It should be like V/4. That otherwise needless 390K does get it off the half-way hump, but not real predictably, and is 0.001uFd really enough to pass the signal around?

[Digital Larry]

Why is the phase-splitter biased to nominal V/2? It should be like V/4. That otherwise needless 390K does get it off the half-way hump, but not real predictably, and is 0.001uFd really enough to pass the signal around?

Hey don't ask me, this is off that Boss Slow Gear schematic I found!

https://www.diystompboxes.com/smfforum/index.php?topic=129364.msg1249964#msg1249964

I'm guessing that it's "close enough" and the actual performance of the circuit is dialed in using the on board trimmers.

DL

[Digital Larry]

I had a feeling it's related to that area around Q4, Q5, D4.   There a lot of capacitively coupled stuff and together with the diode.

What about adding a larger resistor (100MEG/10MEG/1MEG) from the emitters of Q4, Q5 to ground?
I suspect it might come good.

That didn't help, but changing the two emitter followers to "ZTX1048A" from the Generic NPN I'd initially dropped in there seems to be making everyone happy.  Thanks for the suggestions!

DL

[Rob Strand]

That didn't help, but changing the two emitter followers to "ZTX1048A" from the Generic NPN I'd initially dropped in there seems to be making everyone happy.  Thanks for the suggestions!

Very interesting.   I wonder what aspect of the transistor fixed it, maybe a larger leakage param like IS/ISE.   The reason I thought adding the resistor would help is it pins the emitter node voltage to ground.   The whole rectifier kind of floats (caps at base, transistors off at the collectors and reversed-biased diode at the emitters).  When the transistors are off the currents could drop to leakage levels but the transistors are floating at a non-zero voltage.

[Rob Strand]

FYI, I thought I let you know I've managed to get some Defcons popping up on circuit which used a couple of diodes and a opamp (using one of those full-blown Linear Tech opamp models).    The circuit originally had a single transistor in an unconventional connection and that had occasional convergence issues.  The transistor model did change this behaviour.  I then went to the 2xdiode version and the issue became *more* evident.

It seems LT spice occasionally gets convergence issues for numerical reasons.  I tried playing with some .OPTIONS but it didn't change things then (for fun) I added a resistor in a judiciously chosen place, which shouldn't make much difference, and it fixed it.  If I get time I might try to get to the bottom of it.

[Vivek]

Last night, I tried simulating a circuit with only 2 Opamps

I got a Def Con 1

Replaced the Opamps with other Opamp models

No Def Con 1