discrete op ampp compressor issues

[Eddododo]

Hello all.. 

I recently dusted off LT Spice to try to put together a circuit I've wanted to do for years.. but I've also been not thinking about circuits for about 5 years ..

The idea is to do a Hollis Flatliner type compressor,  but the op amp gain stage will be replaced by a sort of primitive discrete op amp.. this signal will then be slammed into the mouth of another single jfet. The goal is to get some nice jfet saturation and compression, with the ability to really dirty it up.. just kind of a vibe.

I'm struggling with 2 or 3 big things

1) I just cant seem to get the photocoupler to respond how I want.. I've done flatliners in the past and rather liked them, and didnt have much trouble with them.
I'm wondering if I'm boogering it up with how I'm handling the Vref and DC state (since the original flatliner is all opamp vref, am I misreading or leaving out something with the signal in my own circuit biased as FETs)... or am I just not driving the LED hard enough.. I have some Macrons vactrol replacements, but I actually just found 3 VTL5C in a component box i had stored.. hasnt helped me so far though

2) I don't seem to be getting any compression going on... I know i stated i have envelope/photocoupler problems, but I have had a few test arrangements that I felt should have worked... Here's another big issue- The light resistance bottoms out a little too high .. the values seem to go down to 20k, 5k, etc, maybe a little lower. This is fine in the flatliner, but Its just barely in the range I need.. the flatliner goes from 220k to ~5k in the feeedback resistance, but mine would be something like 20k to ~5k.. this 'should' still be enough to get me down to unity, but I'm starting to think that the HUGE range of input being brought down to unity on the original flatliner is part of the magic (it has the extra time from 220k to 5k to stay at unity, vs just dipping to unity at the peaks.)   Im starting to think this needs a redesign but let me ask this:
Can I simply use the Jfet gain stages at a 10x scale for the resistors? IE using ~200k  feedback resistor, 100k from source to ground through the capacitor...
In these capacitor-bypassed-source arrangements, do the resistors need to be lower than the existing bias resistors?