"When you promise you are in debt" thay taught me when I was a kid. So here I present my work. I will organize this post in three sections:

* The actual schematic and curves

* Building hints

* Answers to the questions that have arised in this thread so far

So here we go...

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1) Actual Schematic and Curves

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Here is the schematic:

And here the performance curves as simulated with the nominal values indicated:

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2) Building hints:

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Due to the great bandwidth increase with the new implementation, I finally settled for 0.6 msec and 7 kHz bandwidth.

Notice a slight difference between resistors R11 and R27. This is for maximum amplitude flatness. If you use them both equal to either value, you will have a 0.4 dB dip or notch (depending on which value you use) around 5 kHz.

The 20 nF capacitor should be made of two 10 nF in parallel, so you just need to buy two different values only (of course it was impossible to have this capacitor 10 nF due to the high Q of this particular stage which demanded a minimum value higher than 16.3 nF to be realizable, so I settled for the next higher convenient value.)

Each row has a 4.5 dB of gain at every fourth opamp, instead of 26 dB of my former design (so total gain of the two sections is around 9 dB -- the value of 12 dB I posted before was wrong, now it is even better!). As such, I don't think low noise opamps are needed anymore. A TL074 or similar JFET opamp would do fine.

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3) Answers to Questions

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The topology I'm finally using is "7th order 0.05ยบ equiripple phase allpass". I haven't found information on the internet about this so far. I had to go to a 20 year-old book to find the location of the poles for this design, and from that, getting the w's and Q's and then start building the stages. Finally, I used a symbolic math program (Maple) to develop the 2nd order section transfer function and solve it imposing the restrictions of simple capacitor values and minimum insertion loss.

The frequency determining components are the two upper resistors of each 2nd order stage, and the lower resistor of the first order+gain stage. Scale them accordingly and you will move frequency and total delay.

The 10k resistors and its neighbours settle insertion loss AND overall gain flatness, so you can't move them or you will destroy the amplitude response! Unfortunately, there is no easy way to use a photocell or other controlled resistor to tune the filter. I've thought of that so many times, but tight component tolerance preclude doing something like that with this circuit. I've been thinking for along time about how you could build a BBD-less flanger!

Well, that's all for now folks!