Advice needed: idea for addressing clock ticking in flangers

Started by Chico, September 22, 2004, 11:04:02 PM

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In the last month or so, I have taken a keen interest in building a flanger.    

I want to include two bbd lines.  From the abundance of flanger and chorus threads here, it is clear that layout is critical to keep ticking gremlins out of the audio path.

To minimize chances of ticking and other gremlins, I am putting .1 uf ceramic bypass caps on the power pins of every chip, using load resistors and filter capacitors in the power supply lines etc.

I am also building the digital components on one circuit board and analog on another.  The clocks on the digital boards will be connected to the clock inputs on the bbds using shielded jumper wire.

In addition to the above techniques, some have suggested double sided boards and ground planes.  That is not something that I can accomplish at this stage.  

So here is my question.  I have seen in some digital/microprocessor design web sites, the use of diodes to keep analog ADC ground separate from microprocessor/digital ground.

That got me thinking about building a dedicated power supply for my flanger.  The design I came up with includes separate voltage regulators for digital and analog power.  My thought was to use star grounding such that all digital grounds are returned to the digital side of the power supply, all analog grounds are returned to the analog side of the supply, and the analog and digital grounds are connected at the power supply only, by back to back schottky diodes.  

By placing the schottky diodes back to back, the max difference between the grounds would be the diode voltage drop.  If I understand the concept correctly, the separate regulators and diodes may help to keep alot of noise out of the analog power supply.

Has anyone here tried something like this?  Are there any considerations that I am missing here?

For a look at my power supply, see

Any other tips anone can offer to deal with digital and analog circuits in the same design?

Best regards



Not quite, but I often run LFOs from a separate regulator and use micropower amps to keep current spikes to a minimum.  

Like you said, layout is very important.  Separate ground paths, PCB pot connections for LFO and (if necessary) using shielded wire for audio helps a lot.

Edit:  Whoops!  It's morning here and I wasn't paying attention, you're not talking about LFO tick.  Sorry!
"They always say there's nothing new under the sun.  I think that that's a big copout..."  Wayne Shorter


It`s not so much a case of keeping digital away from analog here, since you`re lopassing anyway.
BTW: you will have A and D very close together right at the BBD.

The culprit here is to keep the 2 digital clocks apart from each other!
(2 seperate digi rails - each well decoupled on their own!)
This also means keeping distance between the 2 BBDs
(with their clocks)...
(so: 2 seperate decoupled analog rails for the 2 BBDs + LP, also);

(this is because the clocks themselves don`t harm - until they come
close together, and create their difference-frequencies, which get lower
in the audio-range, the closer you get to the TZ-point, which is just that situation, where almost nothing of the audio signal is left over to
possibly mask any heterodyned beat frequency from the clocks!).

Put the LP filters right at the BBDs (every cm/inch of copper-trace is an antenna!);

use in- and put-lowpass filtering for each BBD separately!

Surround the critical traces with grounded areas (=groundplanes),
in fact don`t leave any PCB space open, but fill everything out with ground.

Now if you use a 5th rail for the main audio, combine all supplies
only at the big PS caps (shunted by 100n),
you won`t need diodes or double-sided PCBs.

Don`t try wanting to put the TZF into a B*ss-sized pedal when not using 2-sided PCB!

To answer one (or 2) of Mark`s questions from a while ago:

IMO it`s the digital crap ("stairs") on the BBD`s in- & outputs, that is responsible for heterodyning before being filtered;
the audio "left & right" of the BBD, "between" input-LP and ouput-LP,
should be handled/dealt with like RF or digital signals;

"Synced" clocks of e.g.: 100kHz and 103kHz riding on the audio,
will still give a 3kHz tone ("whine", when modulated...), when added or subtracted...

so you won`t wanna have a 3kHz lopass "hammer-remedy",
but 2 individual ~50kHz "precaution-therapy" lopasses before combining audio to "overcome" the much-talked-about (incl. by me) TZF-howling.

Since BBDs chop/slice the audio right at their input (& bias-) pin
(as opposed to A/D-converters, where this is technically happening some-where inside the chip after being buffered by a comparator or,
I strictly recommend to individually LP-filter-decouple the input of each BBD, when fed from one single source... :wink:

(from this point on, it`s about time for me again to break back into silence  :P )


Another problem area to watch out for is the quiescent output voltage of the BBD varying with clock rate - this is sometimes, but not always, shown in the datasheets. It can be as much as 1 or 2 volts if you are sweeping the clock over a wide range. And not all BBDs of the same type behave the same either - this is something that could require selecting individual chips. If you avoid fast LFO rates, and stick with sine or triangle waveshape, the problem wouldn't be too noticeable. Otherwise, some sort of variable offset cancellation circuit may be needed.
Regards, Mike


Quote from: ChicoFrom the abundance of flanger and chorus threads here, it is clear that layout is critical to keep ticking gremlins out of the audio path.


Read the article about the "de-tick" mod that Mark Hammer came up with for the Zombie Chorus.  It's on his site,  The tick, IIRC, is related to biasing.


Thanks everyone for your advice and suggestions.  I am going to study this all and hit the workbench over the course of the next week.  

I will let you know how it turns out.

Best regards



Whilst sensible input and output filtering of BBDs is good practice, I often wonder why 2 of my best sounding flangers - Standard Electric Mistress and ADA have virtually none! It's always a compromise I think with flangers.
"I want my meat burned, like St Joan. Bring me pickles and vicious mustards to pierce the tongue like Cardigan's Lancers.".

Peter Snowberg

Has anybody played with slowing the rise time on one or both of the phases of the BBD clock? :)

Adjunt question: Are most common BBDs CMOS or NMOS? I would bet the old SAD1024s are NMOS. Uh oh.... class A MOJO :o
Eschew paradigm obfuscation


Chico/Tom mentioned 2 delaylines
so my excursion was dealing with 2 lines in one "box",
assuming 2 independant clocks.
(since Tom was/is involved in the TZF-discussion...).

It should be taken as a :wink: ,
that I didn`t mention steep (or "heavy") filtering...
(but: proper physical placement for this case.


the SADs are NMOS, as are the MN32XX series,
while the MN30XX series are PMOS;

clock signals "should be reasonably symmetrical and have fairly fast rise and fall times" according to Ray Marston..

read elsewhere, that they gotta be extremely fast, and abolutely 50/50...
(in fact, the buckets are little "sample&hold" circuits)

Peter Snowberg

Thanks for the tech. answer. :D

It would make sense that the whole array should get a perfect 50/50 clock.

I was thinking of "slurring" the signal as it came out of the BBD and thus removing the fastest transients but that would degrade the signal along the rest of the line.

:shock: Hmmmmmm...... Pedal builders would never want to degrade a signal. :mrgreen:

How much does the clock generator have to do with the sound of a BBD pedal???

I've seen several approaches employed including the 3101 clock chip, 4046 PLL, and discrete oscillators that used a gate to invert a single phase clock. That last one doesn't provide perfect non-overlapping phases.

I see two sources of clock distortion possible, overlap/underlap of the clocks and to a much letter degree, asymmetry.
Eschew paradigm obfuscation

Peter Snowberg

Here's a document from Radio Shack that dates from way back when they sold BBDs.  :shock:  :D

It mentions a rise or fall time of 500ns. :mrgreen: I'm just thinking in digital logic terms. Maybe 35ns of clock skew is nothing to worry about. :D
Eschew paradigm obfuscation