Greatly Improved JFET Matcher is here!

[Peter Snowberg]

The actual quote is more like this (I simplified it ;-)

" Everything should be made as simple as possible - but no simpler"

-Eric

I thought that's what that was. It's my favorite Einstein quote. 2nd favorite is "If I had known about the end result of my work, I would have sold shoes."

[zachary vex]

my favorite Einstein quote (of late) is this one:

Things should be made as simple as possible, but no simpler.

works well for designing things.

on edit: oops, i didn't notice someone else had posted this above.

[Rob Strand]

OK while we are getting all scientific an everything I'll show you why two point matching is of no use.  There's been too much misinformation regarding JFET matching and phasers on this group.  A few years back I did a whole heap of analysis and concluded that VP matching was the most important parameter.  The analysis involved writing software to analyse the matching of the all-pass networks with JFETs.

 I posted the results on this group and the conclusions were:

- two point matching is a waste of time
- matching JFET using (hard to do) AC resistance matching is a wast of time
- VP should be used to match JFETs in phasers
- The easiest way to match JFET is to do a VP measurement when the JFET is operated at low currents
- RG's matcher matches the JFETS at much too high a current and doesn't produce optimal results.  The 10M mode of stm's circuit solves this but I think 10M is asking for trouble.  I recommended testing at 10uA or so.

Only the other day we had the thread about using separate trimmers on phasers and the point still hasn't got through.   Am I wasting my breath on this issue?

Here we go (for the last time):

Lets start with stm's measurements:

     Idss Vp      rd0 = Vp/(2*Idss)
01) 4.64 -2.10      226
02) 4.78 -2.24      234      
03) 4.98 -2.26      227
04) 5.61 -2.35      209
05) 5.84 -2.54 *   217
06) 5.87 -2.54 *   216
07) 6.28 -2.61      207
08 ) 6.30 -2.70      214
09) 6.68 -2.69      201
10) 7.02 -2.92      208
11) 7.06 -2.83      200
12) 7.37 -2.91      197
13) 7.65 -2.99 #   195
14) 7.67 -3.00 #   196
15) 8.00 -3.16       198

Average rd0 = 210
min rd0 =195  (-8%)
max rd0 = 234 (11%)
(min rd0 + max rd0)/2 = 215


Incidently rd0 is 1/Yfs  where Yfs is the parameter you see in JFET data sheets.

From this it is immediately clear that despite the very wide variations in Vp and Idss the tolerance of rdss is small ie. the Vp and Idss values are correllated.  There is a physical reason for this as Jfet parameters Idss, Vp and rd0 are all related to the geometry of the Jfet's channel.

The most important point is the tolerance of the (intrinsic) channel resisance rd0 is in the order of capacitance tolerances.

The ac resistance of a JFET is:

   rd(Vgs) =  rd0 / (1 - Vgs/Vp);  Vgs and Vp both signed

With a phaser *all the Jfets* operate off a common VCO.  The
VCO voltage plus the JFET bias network provides a range of gate-source voltages, Vgs.  When the gate-source voltage is close to Vp the ac resistance is high.  When the gate-source voltage moves away from Vp and approaches 0V the ac resistance is low.

When Vgs = 0 the tolerance of the ac resistance is determined
entirely by rd0.  And from the above reasoning the tolerance
on this is fairly low.  Note that the variation in Vp
has no effect.

When vgs is near Vp, the real problem of JFET matching becomes evident.  Consider the case of two JFETs where rds0 = 210ohm for each JFET, VP1 = -4.7V for the first JFET and VP2 = -4.75V for the second JFET.  The two JFETs would be considered fairly well matched. Now suppose the VCO + bias produces a gate source voltage of -4.65V:

For the first JFET:

   rd(-4.65)  = 210 / (1- (-4.65)/(-4.7)) = 19740 ohm

Whereas for the second JFET,

       rds(-4.65) = 210 / (1- (-4.65)/(-4.75))  = 9975 ohm

As is blatently obvious the effect of small mismatches in
Vp produce massive tolerances when the VCO is sweeping the
JFET through the high resistance region, 2 to 1 variation on a good day.
This totally swamps the tiny variations in rds0.

To put this in context two point matching is quite useless.
Vp matching should be the most important thing to match!

The last point is the resistance depends on rd0 and VP and that
Idss is largely an irrelevant parameter. We know the tolerance on rd0 is good so it's measurement is not warranted.  We know Vp is imporant
to match.  To match Vp all you need to do is a measurement at
low Id currents - it doesn't get simpler than taking one measurement.
[edited]

[stm]

Rob, I agree with your conclusions.  The sensitivity analisys around Idss and Vp for Rds is conclusive. Thanks for taking the time to point this.

Considering what you mention, a simpler, efficient and effective way to go would be to use a 1Mohm resistor instead of the 10 Mohm, and omit the OpAmp entirely and measure directly with a decent DVM.  This greatly simplifies the matching fixture to: one resistor, one 9V battery, and a DVM.

As additional information, last night I ended up using a 6 Mohm resistor on my matching fixture (5 x 1.2 Mohm, since I didn't have anything higher available at home).  The voltage difference in Vp when measuring directly across the resistor string or the OpAmp output was consistently 20 mV (like an offset).  So in practice this won't affect matching since it is identical for all devices tested.  This value should be even lower when using a 1 Mohm resistor.  Vor Vp=-3V, the current through the JFET will be 3V/1Mohm = 3 uA.

On another matter, it is really hard to set the LFO offset, since tiny variations on the lower (most negative) voltage greatly affect the sound. The resistance relation of the JFET is highly nonlinear, so I'm moving to study LDR's for now.

Another important hing to notice is that according to this new light, there are two additional matched pairs in my batch: 8 & 9, and 10 & 12.  It is sad to see there are no good candidates for a triplet, not to say a quad.  o building a Phase 90 would require actually 50 or more JFETS to choose from to get a good matched set.

Regards,

STM

[Rob Strand]

and omit the OpAmp entirely

Good idea!  Since the same meter is used it's effect is constant.  It might be wise to add say 220om resistors in series with the drain and gate to prevent damage if the JFET is put in wrong.  A cap might be useful to prevent noise affecting the results. (I've used this method to do quick JFETS measurements for SPICE models.)

it is really hard to set the LFO offset, since tiny variations on the lower (most negative)

That's right on the mark.  While the bias can be made stable (with a regulator), unless you regulate the LFO supply as well the LFO voltage is subject to variations.  The commonly used zeners, < 4.7V, don't actually regulate too well anyway.  All in all when the battery goes flat, or you run of a plug-pack and battery, the phasing quality moves around.   The stability issue is something I looked at when I did my analysis a while back.  The common designs are just acceptable.  One of the EH phasers used a more elaborate scheme with a MOSFET as a reference and MOSFET resisstances (from a 4049 cmos gate) - this also tracks with temperature.  I seemed to remember this design was fairly stable.

It is sad to see there are no good candidates

That's where two bias pots would be useful.

[puretube]

take care to test LDRs under constant surrounding (leaking) light circumstances;
take time - they`re slow (esp. from light to dark, esp. at high R);
don`t forget: LEDs vary too, and are little thermometers...

[stm]

Well, I used an LM78L05 instead of the 4.7V zener, and I powered the LFO IC from this stable 5 volts.  I also connected the JFET sources to these 5V, so everything should be as stable as the LM78L05 allows.

With the original LFO, the sweep seems concentrated on one of the sides, especially at high rates between 2 to 5 Hz, which I dislike.  Is this normal for the original Phase 45?

I made a more complex hypertriangular LFO and I got a more even sweep at high rates, but still too pulsating on one side to my taste.

Any comments/ideas?

[Vsat]

Hi stm,
The FET channel resistance changes most quickly near pinchoff - which also happens to be where the resistance is largest (and corresponds to the sweep "bottom") - so the sweep seems to "decelerate" as the phaser sweeps upward. This may be perceived as a problem -lopsided sweep-  but it is also a part of the "FET phaser sound". If you use linearization techniques the sweep can be warped into something different, and possibly better sounding. But at that point it would be simpler to use OTA's.
Cheers, Mike

[Rob Strand]

Any comments/ideas?

It depends what the actual problem is.  There's two possibilities.  The first is the on and off times for the LFO are not the same.  That can be caused by the LFO opamp not swinging symmetrically around the "centre" point - whis is more probable at low supply voltages.  You can see this by looking at the "square LFO output point on a CRO.  The second possibility is the one Mike mentioned:   tinkering with the hypertriangle shape  is the solution and that could take some experimenting before it sounds right to you.

[d@vide]

...mmm
hey stm
how the new improved tester  will be ?
only a res, battery and dvm how above told or will post a new schem :-)

[stm]

Mike, Rob, thank you for the response.

My LFO is symmetrical and perfectly triangular.  I am using a rail-to-rail opamp fed from the 5V, and the output swing is set to go exactly from 1 to 4 volts, and the reference is 2.5V.  I am using the typical two op-amp triangle generator circuit (one integrator and one comparator with hysteresis).  Then, I am using two additional opamps as precision diodes to introduce gradual clipping on the lower part of the triangle.

This is the schematic:



And these are the curves:



Remember the JFET source are connected to the +5V reference supply, so the hypertriangular output is effectively negative with respect to the JFETs.  Finally, some buffering and offset control is added (not shown in the schematic) to adjust for the exact Vp of the JFETs in use.

Anyway the sweep is much more even than a pure triangular (or the nearly triangular wave you obtain using the single op-amp LFO in the original Phase 45), but still not "right" at high speed settings.

By the way, I adjusted the knee voltages and the limiting resistors according to the theoretical voltage that would produce an exponential resistance variation (i.e. linear when seen on a log resistance graph), and also took into account the effect of the two 10K (i.e. 20k) resistance in parallel with the JFETs.

Mhhh... Maybe I'm too perfectionist and this is just what it is.

Regards,

STM

[Paul Perry (Frostwave)]

My 2 cents:

(1st cent) this fet matching is a great argument for using PWM switched resistors instead.

(2nd cent) the easy way to make a hypertriangle, is to run the triangle thru an overdriven 3080 to make a sine, then full-wave rectify the sine.

I've never built anything with a matched or selected fet, and I hope I never do :wink:

[stm]

Paul, yes, I forgot the full-wave rectified sinusoid.  Anyway making a sinusoidal LFO is not so easy anyway.

Regarding the analog switches, I built a phaser many years ago with them, but the switching introduced some sort of white noise due to PWM leakage in the audio path (in fact, control signal leakage is in the order of 100 mV according to datasheet). I don't know if my circuit was poorly designed or if this is normal in phasers with analog switches.  Also, making the PWM generator has its own complexities as do other methods, so for a Phase 45 I would try to stick with matched JFETs.  But for Phase 90 and higher number of FETs I agree matching is quite a hassle and PWM analog switches would certainly rule.

Mike, any comment on noise when using analog switches with PWM?

Regards,

STM

[Paul Perry (Frostwave)]

I must say, I havn't had much luck with PWM myself, but that was probably due to noise getting into the sawtooth going to the comparator & causing jitter. PWM requires care in construction. MXR seem to have got it to work OK, though. ANd nowadays most low end audio is PWM, believe it or not! (yeah, all those SMT audio amps in phones & computer gear & cheapass boom boxes).

[Vsat]

stm,
For some reason (probably javascript ) aren't able to load any of the schematics/graphs you posted for this thread    so comments will be general.

I assume you have built it so that the triangle LFO waveshape and the transfer function of the "Vgs-waveshaper" are independent of LFO rate - ie. no filtering involved that would change the overall modulation shape  as the rate is varied. In that case, you are probably hearing the normal behavior of a FET phaser. My guess is that the "hypertriangle" "make the  sweep accelerate as it approaches the top" needs some more work.

An alternate approach to "hypertriangle" is to make a voltage-controlled triangle LFO and feed some of the output back to the input... you could try linear but a V/oct rate response would probably give better results. If you have well-matched FET's you could try linearizing the Vgs vs. resistance curve by servoing one FET with an op amp and applying the processed Vgs to the other gates. (BTW what is the proper definition of hypertriangle?)
Also the Eventide Instant Flanger has a CD4066-based plug-in board to convert it into an "Instant Phaser".
Regards, Mike

[stm]

Mike, the links to the images are the following. They should work if you copy-paste them into the address bar of the browser.

http://tinypic.com/1okkrr

http://tinypic.com/1okksj

Yes, there are no frequency dependent elements in the waveshaping circuitry.

So far I think the behaviour I am witnessing is "normal" for phasers (I never really liked phasers, but the Phase 45 samples I've heard are quite sweet, and I really want that "shine on your crazy diamond" sound).  In fact, slow sweeps are definitely more even now than with the original LFO. High sweep rates (those suitable for vibrato) are still better that with the original LFO also, but not "good enough".

So what I'll try next is place a switch for reducing the amplitude of the triangular at high sweep rates before it goes into the shaping section, just as you would do on a Chorus with the Depth control, and see if this helps.

Will keep you informed.

P.D. as for a definition of the hypertriangular, I have not seen a mathematical one yet.  I think the best conceptual representation is the full-wave rectified sine, however you can also have parabolas and exponential functions as well to define the actual curve.

[puretube]

P.D. as for a definition of the hypertriangular, I have not seen a mathematical one yet.  I think the best conceptual representation is the full-wave rectified sine, however you can also have parabolas and exponential functions as well to define the actual curve.

...maybe I`ll find tomorrow - but it is called "parabolic" or "hyperbolic" sometimes...

[Vsat]

stm,
I'll see if the download works later on. Something else that might be the cause of the asymmetry - remember that the modulated allpass stages also provide phase modulation (in the true sense)... this will only be noticeable at the faster LFO rates... so you will get a vibrato component with the faster rates (that is not normally noticed at slower rates). Plus, the "shape" of the vibrato is a function of the LFO waveshape, the Vgs vs resistance curve of the FET, and the waveshaping you are using. Like a BBD, the vibrato is produced only when the phase delay is changing - so a derivative will be needed to determine the actual vibrato "shape" (sinusoidal or not...)
Regards, Mike

[Rob Strand]

I think you might be better off getting rid of the opamp based ideal diodes by using just diodes and changing the reference points to suit.  In this case there may be a problem with the finite reference impedance applying this directly, so you may have to tweak your resistors.  An alternative is to use the opamps to buffer the reference.  The transistions will be smoother and it's highly like this will sound better.

[stm]

Hi, I used one 1N4148 diode to clip the half bottom of the triangular waveform. Not very impressive.  Then I changed the diode for a 1N60 germanium device, readjusted the biasing, and wow! Now I do like the sound within all the speed range (several seconds to fast vibrato). I would describe the overall sound as "organic".  Thanks for the idea Rob. At this point I was able to play for over half an hour without even thinking that it might need some tweaking.

I tried also the "univibing" mod, switching the two 47n caps to 150n and 15n (i.e. 47n*3=150n and 47n/3=15n, which keeps the overal notch frequency identical to the original).  I would describe the sound as being "softer", but don't know for sure it is worth to add a switch, since the difference is rather subtle.

What I am really keeping is a pot that connects the dry and the phased output, which allows gradual transition from DRY, to MILD PHASER, to STOCK PHASER, to PHASER+VIBRATO, to PURE VIBRATO. This is certainly a keeper.

Regards,

STM