Author Topic: CE-2 Subcircuit Explanation?  (Read 8995 times)

Joe Kramer

CE-2 Subcircuit Explanation?
« on: June 28, 2005, 03:05:28 PM »
Hi!

Here's the CE-2 (with thanks to CMW Amps):

http://home.hetnet.nl/~chrisdus/download/ce2.gif

May I ask someone to take the time to explain the function and mechanics of the two transistors, Q4 & Q5, which follow the LFO and precede the clock chip?  Do these serve some buffering/linearizing purpose, or? . . .   What is happening in the circuit here?  Thanks for any help.

Regards,
Joe
Solder first, ask questions later.

www.droolbrothers.com

Vsat

CE-2 Subcircuit Explanation?
« Reply #1 on: June 28, 2005, 08:48:24 PM »
The two transistors to the right of the LFO are used with the MN3102 to produce an approximate "1/X" type of clock response - this is a voltage-controlled clock where the period rather than the frequency is a linear function of the control voltage, in this case the control voltage comes from the LFO. Produces a nicer sounding "bend" of pitch than a simple linear clock would provide (a CD4046 being a good example). A linear clock will tend to "bunch up" most of the pitch change at one end of the LFO sweep, this circuit spreads the pitch change out more evenly. This is most noticeable with large modulation depths. The CE-1 also uses a clock with this kind of response, built with discrete transistors, in some ways better than the one in the CE-2. Perhaps that is one reason the CE-1  is very popular. A very good example of this class of circuit can be seen in the Roland Juno choruses. Also in the EH Echoflanger, EH EM, etc.
Cheers, Mike

Joe Kramer

CE-2 Subcircuit Explanation?
« Reply #2 on: June 28, 2005, 09:20:15 PM »
Hey Mike,

Thanks for your reply!

Quote from: Vsat
The two transistors to the right of the LFO are used with the MN3102 to produce an approximate "1/X" type of clock response - this is a voltage-controlled clock where the period rather than the frequency is a linear function of the control voltage, in this case the control voltage comes from the LFO. Produces a nicer sounding "bend" of pitch than a simple linear clock would provide (a CD4046 being a good example). A linear clock will tend to "bunch up" most of the pitch change at one end of the LFO sweep, this circuit spreads the pitch change out more evenly.


Ah.  I know the LFO puts out a basic triangle wave, rising straight up and falling straight back down.  Are you saying the transistors process this wave into something with a more exponential/logrithmic rise and fall?  And "1/X" is the mathematical equation for exponential response?


Regards,
Joe
Solder first, ask questions later.

www.droolbrothers.com

Vsat

CE-2 Subcircuit Explanation?
« Reply #3 on: June 28, 2005, 10:33:39 PM »
Hi Joe,
Yes, that's the idea. This circuit could be considered as a sort of hypertriangular sweep generator, to use a term which pops up on this forum from time to time.  An exponential clock will also work well here, but the circuit shown is simpler and is happy running on a single 9V supply. The idea is that the clock shouldn't be increasing in frequency at a steady rate, rather it should be increasing in frequency at a steadily increasing rate, as you near the top of sweep. More and more acceleration. A 1/x or expo clock circuit will do this. When used to clock a BBD it gives a more even sounding vibrato in response to a filtered triangle or sine LFO waveform.

Transistor Q5 forms a simple RC  astable oscillator with the MN3102. It is used to discharge the 47 pF timing capacitor, which is charged through the 150K resistor. When the output of the two series-connected inverters (pin 5) in the MN3102 goes high (in response  to the cap charging to the CMOS threshold voltage as monitored by MN3102 pin 7) the transistor turns on and quickly discharges the cap, and the MN3102 output goes low again, turning the transistor off and allowing the cap to re-charge. The cycle repeats at an ultrasonic rate.
 
Q4 on the left is an emitter follower that provides some filtering of the triangle. Immediately after discharge, the diode at the middle of the two 4K7 emitter resistors serves to charge the 47 pF cap rapidly up to a voltage corresponding to the present voltage at the LFO output (minus one Vbe and a diode drop). The 150K resistor takes over at this time and charging proceeds more slowly. Effectively, Q4 serves to shorten or lengthen the clock period by an amount proportional to whatever voltage the LFO output is currently at. Remember that the LFO voltage is changing very slowly compared to the ultrasonic rate the MN3102 operates at. BTW the clock circuit in the Dimension-C is quite similar to this.
Cheers, Mike

nelson

CE-2 Subcircuit Explanation?
« Reply #4 on: June 28, 2005, 11:48:45 PM »
:shock:  :cry:
My project site
Winner of Mar 2009 FX-X

Joe Kramer

CE-2 Subcircuit Explanation?
« Reply #5 on: June 29, 2005, 02:02:36 AM »
Hey Mike,

Wow, this is exactly the explanation I was looking for, but thought I might be imposing to ask.  Thanks!  

Hey Nelson: Don't feel bad!  I barely understand it, but it's interesting!
 
Quote from: Vsat
This circuit could be considered as a sort of hypertriangular sweep generator, to use a term which pops up on this forum from time to time.  An exponential clock will also work well here, but the circuit shown is simpler and is happy running on a single 9V supply. The idea is that the clock shouldn't be increasing in frequency at a steady rate, rather it should be increasing in frequency at a steadily increasing rate, as you near the top of sweep.


Okay, to give it a visual image, which tends to help me grasp these things: instead of a flat-sided triangle, the wave would look more like a bulging dome-shape with a point on top (at least the positive-going segment of the wave).


Quote from: Vsat

Transistor Q5 forms a simple RC  astable oscillator with the MN3102. It is used to discharge the 47 pF timing capacitor, which is charged through the 150K resistor. When the output of the two series-connected inverters (pin 5) in the MN3102 goes high (in response  to the cap charging to the CMOS threshold voltage as monitored by MN3102 pin 7) the transistor turns on and quickly discharges the cap, and the MN3102 output goes low again, turning the transistor off and allowing the cap to re-charge. The cycle repeats at an ultrasonic rate.
 
Q4 on the left is an emitter follower that provides some filtering of the triangle. Immediately after discharge, the diode at the middle of the two 4K7 emitter resistors serves to charge the 47 pF cap rapidly up to a voltage corresponding to the present voltage at the LFO output (minus one Vbe and a diode drop). The 150K resistor takes over at this time and charging proceeds more slowly. Effectively, Q4 serves to shorten or lengthen the clock period by an amount proportional to whatever voltage the LFO output is currently at. Remember that the LFO voltage is changing very slowly compared to the ultrasonic rate the MN3102 operates at.


Okay, the way you're explaining it, it's almost as if the Q5 oscillator circuit is taking very fast samples of the LFO's waveform.  I guess I don't see the thinking behind this yet (not surprising) since it seems easier to modulate the clock of a BBD by changing the resistance (between pins 6 & 7?) as in an analog echo-type circuit.  Since the clock is already a self-contained oscillator circuit, why do we need to hang another oscillator on there?  Isn't it easier to have the LFO's changing voltage drive a transistor acting as a voltage-controlled resistor?  Or do they not do this exactly because the VC resistor circuit simply would not give the exponential response?  Hmm.

Regards,
Joe
Solder first, ask questions later.

www.droolbrothers.com

puretube

CE-2 Subcircuit Explanation?
« Reply #6 on: June 29, 2005, 04:00:28 AM »
I wouldn`t call the MN3101 a selfcontained osc.;
and I wouldn`t call Q5 an extra osc.;

rather: the inverters inside the MN... form an osc. with the help of external components (C/R; or C/{Q5+surroundings} in this case).


More on the CV-to-period: USP4072079 ... (Sharp, 1978)


[btw: Vsat: PM fyi]

Vsat

CE-2 Subcircuit Explanation?
« Reply #7 on: June 29, 2005, 12:00:19 PM »
MN3101/3102 was intended as a self-contained rheostat-controlled BBD clock. Has a lot going for it, it is CMOS so low-power and low-leakage (can use small capacitors), two-phase clock outputs so no CD4013 needed, built-in non-overlap circuit, and fairly decent buffers so it can drive large BBDs like the MN3005 quite easily. Ibanez and Roland both came up with some nice ways to make the MN voltage-controlled with the addition of a few transistors.

Here's two approaches to making  a voltage-controlled oscillator - both use a current source to charge a capacitor, when the capacitor reaches a certain "trip" voltage (as detected by a comparator)  the transistor is briefly turned on to quickly discharge the capacitor.

a) variable voltage-controlled current source with fixed trip voltage - standard synth VCO like ARP Odyssey - the more current the current source puts out, the faster the oscillator runs. If the legal control voltage range is 0 to +10V, it runs slowest at zero volts and fastest at +10V. The freq increases as the CV increases (and the period decreases). Usually set up for a linear or expo response to CV.

b) fixed current source with variable trip voltage - as in EH Echoflanger or EH EM - if the trip voltage is set to just above zero volts, only a short time is required for the cap to reach this level - it is then discharged and the cycle repeats (very quickly). If the trip voltage is set to +10V, the cap takes longer to reach +10V, and the cycle repeats more slowly. The period increases as the control voltage increases (and the freq decreases). This is the "1/x" or voltage-controlled period clock circuit.

The circuit in the CE-2 is most similar to b)
Cheers, Mike
BTW Puretube - thanks for the PM! Will take a look later on.

Joe Kramer

CE-2 Subcircuit Explanation?
« Reply #8 on: June 29, 2005, 03:50:23 PM »
Thanks Mike and Ton for helping with this!

I think some of it is starting to seep through the cracks in my hard skull.

Check me on this: Q5 together with the inverters in IC4 form a kind of exponential VCO.  The LFO outputs the control voltage and Q4 buffers and somewhat shapes this control voltage.  That anywhere in the ballpark?

One last question: I'd like to understand where the buffer proper ends, and the VCO proper begins.  IIUC, R38 is part of the VCO; but is D1 also part of the VCO or does this belong more properly to the buffer?

I want to thank you again, Mike.  I'm hardcopying your explanation for my files.  I also have a whole new appreciation for the wizards behind this circuit!

Many thanks!

Regards,
Joe
Solder first, ask questions later.

www.droolbrothers.com

Vsat

CE-2 Subcircuit Explanation?
« Reply #9 on: June 29, 2005, 08:23:02 PM »
Joe,
If this was the EH EM or Echoflanger R38 would be replaced by a current source made from a PNP transistor... R38 is an essential part of the clock. The MN3102 and Q5 together will oscillate at a constant frequency without Q4 and it's associated components. Q4 buffers the 220K+ 0.01 uF which filters the LFO and provides for  voltage control of the period of the oscillator core built around the MN3102 and Q5. D1 is needed to isolate the output of Q4 once the 47 pF capacitor has charged up to the present LFO voltage ( actually the LFO voltage  minus one Vbe, then attenuated by a factor of two,  then with a further diode drop). The 150K can then charge up the capacitor without any further influence from the buffer, until the 47 pF is discharged again. The LFO with  buffer essentially provides a variable "starting level" for the 47 pF cap.. it charges the cap to this voltage very quickly.. the 150K charges it up much more slowly after this. This variable starting level is the mechanism whereby the clock period is directly controllable by the LFO voltage. Note that when the clock PERIOD is varied in a linear manner (say decreasing by ten uS per second...), the clock FREQUENCY is initially "low", then increases gradually, then speeds up and "goes through the roof" as the period becomes very short.. since freq=1/period. Clocking a delay chip in this manner imparts some very desirable properties.. the A/DA flanger attempts to do this (but in a different manner).

If you are interested in this sort of thing or designing a product I  would highly recommend that you study the PNP + LM311 clock circuit used in the EH flangers - operation  is more obvious than this circuit... also look at the discrete transistor clock for the Roland Juno chorus.. and observe the circuit operation with an oscilloscope if you have one.
Cheers, Mike

Joe Kramer

CE-2 Subcircuit Explanation?
« Reply #10 on: June 29, 2005, 09:34:00 PM »
Hey Mike,

Quote from: Vsat
The LFO with  buffer essentially provides a variable "starting level" for the 47 pF cap.


"Starting level for the cap" --  OH! (out loud). :D  The cap is charging-discharging at an immensely fast rate, but "starting" at a new level each time with the rising and falling voltage of the LFO.  Got it!  Wow, that was was hard, but the lightning bolt I just saw was worth the effort!  8)  :!:

Quote from: Vsat
If you are interested in this sort of thing or designing a product I  would highly recommend that you study the PNP + LM311 clock circuit used in the EH flangers - operation is more obvious than this circuit... also look at the discrete transistor clock for the Roland Juno chorus.. and observe the circuit operation with an oscilloscope if you have one.


Will do!   :D  Many many thanks!

Regards,
Joe

PS: On a slightly related topic, I was reading up about capacitor types, and came across the fact that polystyrene caps are highly desirable in timing/VCO circuits.  Any experience using a polysty for an app like this--in this case, the 47pf timing cap?  Just wondering if it would be of any benefit. . . .
Solder first, ask questions later.

www.droolbrothers.com

Vsat

CE-2 Subcircuit Explanation?
« Reply #11 on: June 29, 2005, 10:10:20 PM »
Joe,
You got it.
Wouldn't hurt to use as polystyrene or silver-mica in there... but a mylar or even a ceramic would be fine. NPO ceramic would have the best temperature stability if you do end up using ceramic. Might even be worthwhile trying a 50 pF or 100 pF trimmer capacitor and seeing how you like the sound.
Cheers, Mike

Vsat

CE-2 Subcircuit Explanation?
« Reply #12 on: June 30, 2005, 01:07:24 AM »
Puretube,
Thanks for pointing out the Sharp patent - that explains the "why" of  1/x clocks very well.

And the system Sharp describes is  what is used in the Roland  Juno(s), probably also the Jupiter-4, and forms the heart of the Dimension-C and D. The only difference is that Sharp uses a PUT-based clock, while the Juno etc use bipolar transistors/op amps/CD4069 etc. Fascinating read.
Regards, Mike

Joe Kramer

CE-2 Subcircuit Explanation?
« Reply #13 on: June 30, 2005, 05:17:15 PM »
Ton, ditto thanks for the patent!

Mike,

My interest in the circuit was because a) I started out wanting to mod the CE2/CE3 for vibrato and b) because previously I only understood the LDR method of modulating a BBD clock.   I was basically put-off from that part of the circuit for lack of understanding.  But thanks to your explanations, I'm a few milliamps (milliwatts?) smarter than I was yesterday.  

BTW, the LDR method seems to have a sort of built in expo curve to it, at least to my ear, maybe due to the inherent slowness of the resistor's response.  Not sure if that would prove out under strict testing though.  Anyway, now that I understand the VCO method, time to experiment!

Regards,
Joe
Solder first, ask questions later.

www.droolbrothers.com

Vsat

CE-2 Subcircuit Explanation?
« Reply #14 on: July 01, 2005, 11:06:44 AM »
Joe,
Might be worthwhile to take a look at the schematics for the various Ibanez flangers/choruses/analog delays. The MN3101/3102 is used in many of these, several different approaches to voltage-control are taken.
Mike

kugua

Re: CE-2 Subcircuit Explanation?
« Reply #15 on: October 08, 2005, 10:42:15 PM »
how can i change the Q5 DIScharger frequence?change the 47pf?or another idea?the calculate expressions is what ?very interested
no